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drm/amd/display: Enable more IPS options

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[why]
To help isolate static screen and
video playback tests, we want to enable
an IPS option to allow IPS only on D3 cycle.

[how]
Add DISABLE_DYNAMIC and DISABLE_ALL
IPS disable flags for user control.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Joon Kim
2023-10-16 11:35:56 -04:00
committed by Alex Deucher
parent eacfdc362d
commit 92e11f0159
3 changed files with 12 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
View File

@@ -814,7 +814,8 @@ static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
struct dc *dc = clk_mgr_base->ctx->dc;
uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
if (dc->config.disable_ips == 0) {
if (dc->config.disable_ips == DMUB_IPS_ENABLE ||
dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {
val |= DMUB_IPS1_ALLOW_MASK;
val |= DMUB_IPS2_ALLOW_MASK;
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
@@ -1114,7 +1115,7 @@ void dcn35_clk_mgr_construct(
dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
smu_dpm_clks.dpm_clks);
if (ctx->dc->config.disable_ips == 0) {
if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
bool ips_support = false;
/*avoid call pmfw at init*/
@@ -1127,7 +1128,7 @@ void dcn35_clk_mgr_construct(
ctx->dc->debug.disable_hpo_power_gate = false;
} else {
/*let's reset the config control flag*/
ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/
ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
}
}
}

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -4887,7 +4887,7 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)
if (dc->debug.disable_idle_power_optimizations)
return;
if (dc->caps.ips_support && dc->config.disable_ips)
if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
return;
if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
@@ -4908,7 +4908,7 @@ bool dc_dmub_is_ips_idle_state(struct dc *dc)
if (dc->debug.disable_idle_power_optimizations)
return false;
if (!dc->caps.ips_support || dc->config.disable_ips)
if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL))
return false;
if (dc->hwss.get_idle_state)

9
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@@ -619,9 +619,12 @@ enum dmub_lvtma_status_bit {
};
enum dmub_ips_disable_type {
DMUB_IPS_DISABLE_IPS1 = 1,
DMUB_IPS_DISABLE_IPS2 = 2,
DMUB_IPS_DISABLE_IPS2_Z10 = 3,
DMUB_IPS_ENABLE = 0,
DMUB_IPS_DISABLE_ALL = 1,
DMUB_IPS_DISABLE_IPS1 = 2,
DMUB_IPS_DISABLE_IPS2 = 3,
DMUB_IPS_DISABLE_IPS2_Z10 = 4,
DMUB_IPS_DISABLE_DYNAMIC = 5,
};
#define DMUB_IPS1_ALLOW_MASK 0x00000001