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drm/amd/display: Remove unused read_ono_state function from Hwss module

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[Why]
The functions read_ono_state are no longer in use and have been identified
as redundant.
Removing them helps streamline the codebase and improve maintainability by
eliminating unnecessary code.

[How]
These unused functions were removed from Hwss module, ensuring that no
functionality is affected, and the code is simplified.

Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Karthi Kandasamy
2024-12-20 08:46:45 +01:00
committed by Alex Deucher
parent 4caacd1671
commit 92d100378c
2 changed files with 0 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

85
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@@ -127,91 +127,6 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx)
mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
}
struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc, uint8_t region)
{
struct dce_hwseq *hws = dc->hwseq;
struct ips_ono_region_state state = {0, 0};
switch (region) {
case 0:
/* dccg, dio, dcio */
REG_GET_2(DOMAIN22_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 1:
/* dchubbub, dchvm, dchubbubmem */
REG_GET_2(DOMAIN23_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 2:
/* mpc, opp, optc, dwb */
REG_GET_2(DOMAIN24_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 3:
/* hpo */
REG_GET_2(DOMAIN25_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 4:
/* dchubp0, dpp0 */
REG_GET_2(DOMAIN0_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 5:
/* dsc0 */
REG_GET_2(DOMAIN16_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 6:
/* dchubp1, dpp1 */
REG_GET_2(DOMAIN1_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 7:
/* dsc1 */
REG_GET_2(DOMAIN17_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 8:
/* dchubp2, dpp2 */
REG_GET_2(DOMAIN2_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 9:
/* dsc2 */
REG_GET_2(DOMAIN18_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 10:
/* dchubp3, dpp3 */
REG_GET_2(DOMAIN3_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
case 11:
/* dsc3 */
REG_GET_2(DOMAIN19_PG_STATUS,
DOMAIN_DESIRED_PWR_STATE, &state.desire_pwr_state,
DOMAIN_PGFSM_PWR_STATUS, &state.current_pwr_state);
break;
default:
break;
}
return state;
}
void dcn401_init_hw(struct dc *dc)
{
struct abm **abms = dc->res_pool->multiple_abms;

2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
View File

@@ -63,8 +63,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);
bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);
struct ips_ono_region_state dcn401_read_ono_state(struct dc *dc,
uint8_t region);
void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,
const struct pipe_ctx *top_pipe_to_program);