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drm/amd/display: Fix uninitialized variables in dcn401 and dml21

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This fixes 12 UNINIT issues reported by Coverity.

Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung
2024-04-25 14:39:11 -06:00
committed by Alex Deucher
parent b3f4ee8e4a
commit 9243e0e206
4 changed files with 10 additions and 8 deletions
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4
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
View File

@@ -474,7 +474,7 @@ static void read_gamut_remap(struct mpc *mpc,
enum mpcc_gamut_remap_id gamut_remap_block_id,
uint32_t *mode_select)
{
struct color_matrices_reg gamut_regs;
struct color_matrices_reg gamut_regs = {0};
struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
switch (gamut_remap_block_id) {
@@ -563,7 +563,7 @@ void mpc401_get_gamut_remap(struct mpc *mpc,
int mpcc_id,
struct mpc_grph_gamut_adjustment *adjust)
{
uint16_t arr_reg_val[12];
uint16_t arr_reg_val[12] = {0};
uint32_t mode_select;
read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust->mpcc_gamut_remap_block_id, &mode_select);

4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
View File

@@ -114,7 +114,7 @@ static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_sta
struct dml2_per_plane_programming *pln_prog = NULL;
struct dml2_per_stream_programming *stream_prog = NULL;
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
int num_pipes;
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
@@ -274,7 +274,7 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
{
unsigned int num_pipes, dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
struct dml2_per_plane_programming *pln_prog = NULL;
struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL;

4
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
View File

@@ -11060,8 +11060,8 @@ void dml2_core_calcs_get_dpte_row_height(
unsigned int MacroTileWidthC;
unsigned int MacroTileHeightY;
unsigned int MacroTileHeightC;
bool surf_linear_128_l;
bool surf_linear_128_c;
bool surf_linear_128_l = 0;
bool surf_linear_128_c = 0;
CalculateBytePerPixelAndBlockSizes(
SourcePixelFormat,

6
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
View File

@@ -465,7 +465,9 @@ void dcn401_populate_mcm_luts(struct dc *dc,
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g;
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b;
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r;
enum MCM_LUT_XABLE shaper_xable, lut3d_xable, lut1d_xable;
enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE;
dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable);
@@ -937,7 +939,7 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dccg *dccg = dc->res_pool->dccg;
enum phyd32clk_clock_source phyd32clk;
int dp_hpo_inst;
int dp_hpo_inst = 0;
unsigned int tmds_div = PIXEL_RATE_DIV_NA;
unsigned int unused_div = PIXEL_RATE_DIV_NA;