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Merge branches 'clk-microchip' and 'clk-qcom' into clk-next

Browse Source 
* clk-microchip:
  clk: at91: keep securam node alive while mapping it
  clk: at91: sama7d65: add peripheral clock for I3C
  clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix
  clk: at91: sam9x7: Fix gmac_gclk clock definition
  clk: at91: sam9x7: Rename macb0_clk to gmac_clk
  clk: at91: sam9x7: Remove gmac peripheral clock with ID 67
  clk: microchip: rename clk-core to clk-pic32

* clk-qcom: (32 commits)
  clk: qcom: regmap-phy-mux: Rework the implementation
  clk: qcom: a53: Corrected frequency multiplier for 1152MHz
  clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC
  clk: qcom: gdsc: Support enabling interconnect path for power domain
  dt-bindings: clock: qcom,milos-camcc: Document interconnect path
  interconnect: Add devm_of_icc_get_by_index() as exported API for users
  clk: qcom: camcc-x1p42100: Add support for camera clock controller
  clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks
  clk: qcom: videocc-x1p42100: Add support for video clock controller
  dt-bindings: clock: qcom: Add X1P42100 camera clock controller
  dt-bindings: clock: qcom: Add X1P42100 video clock controller
  clk: qcom: nord: negcc: add support for the USB2 PHY reset
  dt-bindings: clock: qcom: add the definition for the USB2 PHY reset
  clk: qcom: clk-rpmh: Make all VRMs optional
  clk: qcom: Add support for global clock controller on Hawi
  clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL
  clk: qcom: Add Hawi TCSR clock controller driver
  clk: qcom: rpmh: Add support for Hawi RPMH clocks
  dt-bindings: clock: qcom: Add Hawi global clock controller
  dt-bindings: clock: qcom: Add Hawi TCSR clock controller
  ...
This commit is contained in:
Stephen Boyd
2026-06-25 07:55:47 -07:00
parent db810874e5 19ec63c4ef 9e5c34544e
commit 92010229c4
53 changed files with 11335 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
View File

@@ -42,12 +42,6 @@ properties:
- const: cfg_ahb_clk
- const: gcc_disp_gpll0_div_clk_src
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
@@ -58,18 +52,16 @@ properties:
A phandle to an OPP node describing the power domain's performance point.
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
@@ -101,6 +93,7 @@ examples:
power-domains = <&rpmpd SM6125_VDDCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

63
Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml Normal file
View File

@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,hawi-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Hawi
maintainers:
- Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Hawi.
See also: include/dt-bindings/clock/qcom,hawi-gcc.h
properties:
compatible:
const: qcom,hawi-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: UFS PHY RX symbol 0 clock
- description: UFS PHY RX symbol 1 clock
- description: UFS PHY TX symbol 0 clock
- description: USB3 PHY wrapper pipe clock
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,hawi-gcc";
reg = <0x00100000 0x1f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

1
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
View File

@@ -25,6 +25,7 @@ properties:
compatible:
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5332-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq6018-cmn-pll
- qcom,ipq8074-cmn-pll

68
Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml Normal file
View File

@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ9650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ9650
See also:
include/dt-bindings/clock/qcom,ipq9650-gcc.h
include/dt-bindings/reset/qcom,ipq9650-gcc.h
properties:
compatible:
const: qcom,ipq9650-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE30 PHY0 pipe clock source
- description: PCIE30 PHY1 pipe clock source
- description: PCIE30 PHY2 pipe clock source
- description: PCIE30 PHY3 pipe clock source
- description: PCIE30 PHY4 pipe clock source
- description: USB PCIE wrapper pipe clock source
- description: NSS common clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq9650-gcc";
reg = <0x01800000 0x40000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie30_phy0_pipe_clk>,
<&pcie30_phy1_pipe_clk>,
<&pcie30_phy2_pipe_clk>,
<&pcie30_phy3_pipe_clk>,
<&pcie30_phy4_pipe_clk>,
<&usb3phy_0_cc_pipe_clk>,
<&nss_cmn_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
View File

@@ -44,7 +44,7 @@ required:
- power-domains
- '#power-domain-cells'
unevaluatedProperties: false
additionalProperties: false
examples:
- |

8
Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml
View File

@@ -25,6 +25,10 @@ properties:
- description: Sleep clock source
- description: Camera AHB clock from GCC
interconnects:
items:
- description: Interconnect path to enable the MultiMedia NoC
required:
- compatible
- clocks
@@ -37,12 +41,16 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
clock-controller@adb0000 {
compatible = "qcom,milos-camcc";
reg = <0x0adb0000 0x40000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

61
Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml Normal file
View File

@@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-gxclkctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Power Domain Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC). This module provides the power domains control
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
See also:
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
properties:
compatible:
enum:
- qcom,milos-gxclkctl
reg:
maxItems: 1
power-domains:
description:
Power domains required for the clock controller to operate
items:
- description: GFX power domain
- description: GPUCC(CX) power domain
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- power-domains
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d64000 {
compatible = "qcom,milos-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
power-domains = <&rpmhpd RPMHPD_GFX>,
<&gpucc 0>;
#power-domain-cells = <1>;
};
};
...

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@@ -19,6 +19,7 @@ properties:
enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk

3
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -20,6 +20,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
include/dt-bindings/clock/qcom,x1p42100-videocc.h
properties:
compatible:
@@ -32,6 +33,7 @@ properties:
- qcom,sm8650-videocc
- qcom,sm8750-videocc
- qcom,x1e80100-videocc
- qcom,x1p42100-videocc
clocks:
items:
@@ -70,6 +72,7 @@ allOf:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
- qcom,x1p42100-videocc
then:
required:
- required-opps

2
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@@ -17,6 +17,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,hawi-tcsrcc.h
- include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
@@ -28,6 +29,7 @@ properties:
- enum:
- qcom,eliza-tcsr
- qcom,glymur-tcsr
- qcom,hawi-tcsrcc
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc

1
Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
View File

@@ -23,6 +23,7 @@ properties:
compatible:
enum:
- qcom,x1e80100-camcc
- qcom,x1p42100-camcc
reg:
maxItems: 1

2
drivers/clk/at91/pmc.c
View File

@@ -180,9 +180,9 @@ static int __init pmc_register_ops(void)
of_node_put(np);
return -ENODEV;
}
of_node_put(np);
at91_pmc_backup_suspend = of_iomap(np, 0);
of_node_put(np);
if (!at91_pmc_backup_suspend) {
pr_warn("%s(): unable to map securam\n", __func__);
return -ENOMEM;

21
drivers/clk/at91/sam9x7.c
View File

@@ -387,7 +387,7 @@ static const struct {
{ .n = "dma0_clk", .id = 20, },
{ .n = "uhphs_clk", .id = 22, },
{ .n = "udphs_clk", .id = 23, },
{ .n = "macb0_clk", .id = 24, },
{ .n = "gmac_clk", .id = 24, },
{ .n = "lcd_clk", .id = 25, },
{ .n = "sdmmc1_clk", .id = 26, },
{ .n = "ssc_clk", .id = 28, },
@@ -420,7 +420,6 @@ static const struct {
{ .n = "lvdsc_clk", .id = 56, },
{ .n = "pit64b1_clk", .id = 58, },
{ .n = "puf_clk", .id = 59, },
{ .n = "gmactsu_clk", .id = 67, },
};
/*
@@ -569,6 +568,15 @@ static const struct {
.pp_chg_id = INT_MIN,
},
{
.n = "gmac_gclk",
.id = 24,
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
.pp_mux_table = { 6, 8, },
.pp_count = 2,
.pp_chg_id = INT_MIN,
},
{
.n = "lcd_gclk",
.id = 25,
@@ -702,15 +710,6 @@ static const struct {
.pp_count = 1,
.pp_chg_id = INT_MIN,
},
{
.n = "gmac_gclk",
.id = 67,
.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
.pp_mux_table = { 6, 8, },
.pp_count = 2,
.pp_chg_id = INT_MIN,
},
};
static void __init sam9x7_pmc_setup(struct device_node *np)

1
drivers/clk/at91/sama7d65.c
View File

@@ -677,6 +677,7 @@ static struct {
{ .n = "uhphs_clk", .p = PCK_PARENT_HW_MCK5, .id = 101, },
{ .n = "dsi_clk", .p = PCK_PARENT_HW_MCK3, .id = 103, },
{ .n = "lvdsc_clk", .p = PCK_PARENT_HW_MCK3, .id = 104, },
{ .n = "i3cc_clk", .p = PCK_PARENT_HW_MCK8, .id = 105, },
};
/*

2
drivers/clk/microchip/Makefile
View File

@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
obj-$(CONFIG_COMMON_CLK_PIC32) += clk-pic32.o
obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o
obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o

15
drivers/clk/microchip/clk-mpfs-ccc.c
View File

@@ -32,6 +32,7 @@
#define MPFS_CCC_FIXED_DIV 4
#define MPFS_CCC_OUTPUTS_PER_PLL 4
#define MPFS_CCC_REFS_PER_PLL 2
#define MPFS_CCC_NUM_CLKS 16
struct mpfs_ccc_data {
void __iomem **pll_base;
@@ -178,7 +179,7 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
out_hw->id);
data->hw_data.hws[out_hw->id - 2] = &out_hw->divider.hw;
data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
}
return 0;
@@ -231,17 +232,9 @@ static int mpfs_ccc_probe(struct platform_device *pdev)
{
struct mpfs_ccc_data *clk_data;
void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)];
unsigned int num_clks;
int ret;
/*
* If DLLs get added here, mpfs_ccc_register_outputs() currently packs
* sparse clock IDs in the hws array
*/
num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) +
ARRAY_SIZE(mpfs_ccc_pll1out_clks);
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, MPFS_CCC_NUM_CLKS),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
@@ -255,7 +248,7 @@ static int mpfs_ccc_probe(struct platform_device *pdev)
return PTR_ERR(pll_base[1]);
clk_data->pll_base = pll_base;
clk_data->hw_data.num = num_clks;
clk_data->hw_data.num = MPFS_CCC_NUM_CLKS;
clk_data->dev = &pdev->dev;
ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,

2
drivers/clk/microchip/clk-core.c → drivers/clk/microchip/clk-pic32.c
View File

@@ -11,7 +11,7 @@
#include <linux/iopoll.h>
#include <linux/platform_data/pic32.h>
#include "clk-core.h"
#include "clk-pic32.h"
/* OSCCON Reg fields */
#define OSC_CUR_MASK 0x07

0
drivers/clk/microchip/clk-core.h → drivers/clk/microchip/clk-pic32.h
View File

2
drivers/clk/microchip/clk-pic32mzda.c
View File

@@ -14,7 +14,7 @@
#include <linux/platform_device.h>
#include <asm/traps.h>
#include "clk-core.h"
#include "clk-pic32.h"
/* FRC Postscaler */
#define OSC_FRCDIV_MASK 0x07

48
drivers/clk/qcom/Kconfig
View File

@@ -200,6 +200,17 @@ config CLK_X1E80100_TCSRCC
Support for the TCSR clock controller on X1E80100 devices.
Say Y if you want to use peripheral devices such as SD/UFS.
config CLK_X1P42100_CAMCC
tristate "X1P42100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_X1E80100_GCC
default m if ARCH_QCOM
help
Support for the camera clock controller on Qualcomm Technologies, Inc.
X1P42100 devices.
Say Y if you want to support camera devices and camera functionality
such as capturing pictures.
config CLK_X1P42100_GPUCC
tristate "X1P42100 Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -209,6 +220,17 @@ config CLK_X1P42100_GPUCC
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config CLK_X1P42100_VIDEOCC
tristate "X1P42100 Video Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_X1E80100_GCC
default m if ARCH_QCOM
help
Support for the video clock controller on Qualcomm Technologies, Inc.
X1P42100 devices.
Say Y if you want to support video devices and functionality such as
video encode/decode.
config CLK_QCM2290_GPUCC
tristate "QCM2290 Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -296,6 +318,22 @@ config QCOM_CLK_RPMH
Say Y if you want to support the clocks exposed by RPMh on
platforms such as SDM845.
config CLK_HAWI_GCC
tristate "Hawi Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on Hawi devices.
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SD/eMMC, PCIe, etc.
config CLK_HAWI_TCSRCC
tristate "Hawi TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
help
Support for the TCSR clock controller on Hawi devices.
Say Y if you want to use peripheral devices such as PCIe, USB, UFS.
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
depends on ARM || COMPILE_TEST
@@ -434,6 +472,16 @@ config IPQ_GCC_9574
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9574.
config IPQ_GCC_9650
tristate "IPQ9650 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
help
Support for global clock controller on ipq9650 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9650.
config IPQ_NSSCC_5424
tristate "IPQ5424 NSS Clock Controller"
depends on ARM64 || COMPILE_TEST

7
drivers/clk/qcom/Makefile
View File

@@ -29,6 +29,8 @@ obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
obj-$(CONFIG_CLK_HAWI_GCC) += gcc-hawi.o
obj-$(CONFIG_CLK_HAWI_TCSRCC) += tcsrcc-hawi.o
obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
@@ -42,7 +44,9 @@ obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GPUCC) += gpucc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
obj-$(CONFIG_CLK_X1P42100_CAMCC) += camcc-x1p42100.o
obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o
obj-$(CONFIG_CLK_X1P42100_VIDEOCC) += videocc-x1p42100.o
obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_5424) += apss-ipq5424.o
@@ -57,6 +61,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_GCC_9650) += gcc-ipq9650.o
obj-$(CONFIG_IPQ_NSSCC_5424) += nsscc-ipq5424.o
obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
@@ -189,7 +194,7 @@ obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o
obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
obj-$(CONFIG_SM_GPUCC_8750) += gpucc-sm8750.o gxclkctl-kaanapali.o
obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o
obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o gxclkctl-kaanapali.o
obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o

2
drivers/clk/qcom/a53-pll.c
View File

@@ -20,7 +20,7 @@
static const struct pll_freq_tbl a53pll_freq[] = {
{ 998400000, 52, 0x0, 0x1, 0 },
{ 1094400000, 57, 0x0, 0x1, 0 },
{ 1152000000, 62, 0x0, 0x1, 0 },
{ 1152000000, 60, 0x0, 0x1, 0 },
{ 1209600000, 63, 0x0, 0x1, 0 },
{ 1248000000, 65, 0x0, 0x1, 0 },
{ 1363200000, 71, 0x0, 0x1, 0 },

7
drivers/clk/qcom/camcc-milos.c
View File

@@ -30,6 +30,11 @@ enum {
DT_IFACE,
};
/* Need to match the order of interconnects in DT binding */
enum {
DT_ICC_TOP_GDSC,
};
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
@@ -1971,6 +1976,8 @@ static struct gdsc cam_cc_camss_top_gdsc = {
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
.needs_icc = true,
.icc_path_index = DT_ICC_TOP_GDSC,
};
static struct clk_regmap *cam_cc_milos_clocks[] = {

64
drivers/clk/qcom/camcc-x1e80100.c
View File

@@ -1052,6 +1052,31 @@ static struct clk_rcg2 cam_cc_mclk7_clk_src = {
},
};
static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_CAM_CC_PLL8_OUT_EVEN, 8, 0, 0),
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
.cmd_rcgr = 0x13938,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
@@ -2182,6 +2207,42 @@ static struct clk_branch cam_cc_mclk7_clk = {
},
};
static struct clk_branch cam_cc_qdss_debug_clk = {
.halt_reg = 0x13a64,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13a64,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_qdss_debug_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
.halt_reg = 0x13a68,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13a68,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_qdss_debug_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sfe_0_clk = {
.halt_reg = 0x133c0,
.halt_check = BRANCH_HALT,
@@ -2398,6 +2459,9 @@ static struct clk_regmap *cam_cc_x1e80100_clocks[] = {
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,

2223
drivers/clk/qcom/camcc-x1p42100.c Normal file
View File

File diff suppressed because it is too large Load Diff

6
drivers/clk/qcom/clk-alpha-pll.h
View File

@@ -31,6 +31,7 @@ enum {
CLK_ALPHA_PLL_TYPE_PONGO_EKO_T = CLK_ALPHA_PLL_TYPE_PONGO_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
@@ -198,16 +199,19 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops
#define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops
#define clk_alpha_pll_taycan_eha_t_ops clk_alpha_pll_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops
#define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo_ops
#define clk_alpha_pll_fixed_taycan_eha_t_ops clk_alpha_pll_fixed_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops
#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid_evo_ops
#define clk_alpha_pll_postdiv_taycan_eha_t_ops clk_alpha_pll_postdiv_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_pongo_elu_ops;
#define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops
@@ -246,6 +250,8 @@ void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
clk_lucid_evo_pll_configure(pll, regmap, config)
#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \
clk_lucid_evo_pll_configure(pll, regmap, config)
#define clk_taycan_eha_t_pll_configure(pll, regmap, config) \
clk_lucid_evo_pll_configure(pll, regmap, config)
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);

58
drivers/clk/qcom/clk-regmap-phy-mux.c
View File

@@ -15,48 +15,66 @@
#define PHY_MUX_PHY_SRC 0
#define PHY_MUX_REF_SRC 2
#define XO_RATE 19200000UL
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
{
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
}
static int phy_mux_is_enabled(struct clk_hw *hw)
static unsigned long phy_mux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
unsigned int val;
u32 val;
regmap_read(clkr->regmap, phy_mux->reg, &val);
val = FIELD_GET(PHY_MUX_MASK, val);
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
return val == PHY_MUX_PHY_SRC;
switch (FIELD_GET(PHY_MUX_MASK, val)) {
case PHY_MUX_PHY_SRC:
return ULONG_MAX;
case PHY_MUX_REF_SRC:
return XO_RATE;
default:
return 0;
}
}
static int phy_mux_enable(struct clk_hw *hw)
static int phy_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
if (req->rate == XO_RATE || req->rate == ULONG_MAX)
return 0;
return -EINVAL;
}
static int phy_mux_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
u32 val;
return regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
}
static void phy_mux_disable(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
switch (rate) {
case XO_RATE:
val = PHY_MUX_REF_SRC;
break;
case ULONG_MAX:
val = PHY_MUX_PHY_SRC;
break;
default:
return -EINVAL;
}
regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
FIELD_PREP(PHY_MUX_MASK, val));
return 0;
}
const struct clk_ops clk_regmap_phy_mux_ops = {
.enable = phy_mux_enable,
.disable = phy_mux_disable,
.is_enabled = phy_mux_is_enabled,
.recalc_rate = phy_mux_recalc_rate,
.determine_rate = phy_mux_determine_rate,
.set_rate = phy_mux_set_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);

41
drivers/clk/qcom/clk-rpmh.c
View File

@@ -66,8 +66,6 @@ struct clk_rpmh {
struct clk_rpmh_desc {
struct clk_hw **clks;
size_t num_clks;
/* RPMh clock clkaN are optional for this platform */
bool clka_optional;
};
static DEFINE_MUTEX(rpmh_clk_lock);
@@ -409,7 +407,9 @@ DEFINE_CLK_RPMH_VRM(clk5, _a2_e0, "C5A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk6, _a2_e0, "C6A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk7, _a2_e0, "C7A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk8, _a2_e0, "C8A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk9, _a2_e0, "C9A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk7, _a4_e0, "C7A_E0", 4);
DEFINE_CLK_RPMH_VRM(clk11, _a4_e0, "C11A_E0", 4);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
@@ -697,7 +697,6 @@ static struct clk_hw *sm8550_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
.clks = sm8550_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *sm8650_rpmh_clocks[] = {
@@ -729,7 +728,6 @@ static struct clk_hw *sm8650_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
.clks = sm8650_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
@@ -899,7 +897,6 @@ static struct clk_hw *sm8750_rpmh_clocks[] = {
static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
.clks = sm8750_rpmh_clocks,
.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
.clka_optional = true,
};
static struct clk_hw *glymur_rpmh_clocks[] = {
@@ -984,6 +981,36 @@ static const struct clk_rpmh_desc clk_rpmh_nord = {
.num_clks = ARRAY_SIZE(nord_rpmh_clocks),
};
static struct clk_hw *hawi_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_DIV_CLK1] = &clk_rpmh_clk11_a4_e0.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2_e0.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_e0_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a4_e0.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a4_e0_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2_e0.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_e0_ao.hw,
[RPMH_LN_BB_CLK4] = &clk_rpmh_clk9_a2_e0.hw,
[RPMH_LN_BB_CLK4_A] = &clk_rpmh_clk9_a2_e0_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_clk1_a1_e0.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_e0_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_clk2_a1_e0.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_e0_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a2_e0.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_e0_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2_e0.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_e0_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_hawi = {
.clks = hawi_rpmh_clocks,
.num_clks = ARRAY_SIZE(hawi_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -1027,8 +1054,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
if (!res_addr) {
hw_clks[i] = NULL;
if (desc->clka_optional &&
!strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1))
if (rpmh_clk->res_addr == CLK_RPMH_VRM_EN_OFFSET)
continue;
dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
@@ -1075,6 +1101,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,eliza-rpmh-clk", .data = &clk_rpmh_eliza},
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,hawi-rpmh-clk", .data = &clk_rpmh_hawi},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
{ .compatible = "qcom,nord-rpmh-clk", .data = &clk_rpmh_nord},

2
drivers/clk/qcom/dispcc-x1e80100.c
View File

@@ -1634,7 +1634,7 @@ static const struct regmap_config disp_cc_x1e80100_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x11008,
.max_register = 0xf004, /* 0x10000, 0x10004 and maybe others are for TZ */
.fast_io = true,
};

3657
drivers/clk/qcom/gcc-hawi.c Normal file
View File

File diff suppressed because it is too large Load Diff

3445
drivers/clk/qcom/gcc-ipq9650.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/clk/qcom/gcc-nord.c
View File

@@ -1850,7 +1850,7 @@ static const struct regmap_config gcc_nord_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data gcc_nord_driver_data = {
static const struct qcom_cc_driver_data gcc_nord_driver_data = {
.dfs_rcgs = gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
};

33
drivers/clk/qcom/gdsc.c
View File

@@ -7,6 +7,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/interconnect.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
@@ -147,6 +148,12 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
return ret;
}
if (status == GDSC_ON) {
ret = icc_set_bw(sc->icc_path, 1, 1);
if (ret)
goto err_disable_supply;
}
ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
/* If disabling votable gdscs, don't poll on status */
@@ -177,6 +184,12 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
ret = gdsc_poll_status(sc, status);
WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
if (!ret && status == GDSC_OFF) {
ret = icc_set_bw(sc->icc_path, 0, 0);
if (ret)
return ret;
}
if (!ret && status == GDSC_OFF && sc->rsupply) {
ret = regulator_disable(sc->rsupply);
if (ret < 0)
@@ -184,6 +197,12 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
}
return ret;
err_disable_supply:
if (status == GDSC_ON && sc->rsupply)
regulator_disable(sc->rsupply);
return ret;
}
static inline int gdsc_deassert_reset(struct gdsc *sc)
@@ -584,6 +603,20 @@ int gdsc_register(struct gdsc_desc *desc,
if (!data->domains)
return -ENOMEM;
for (i = 0; i < num; i++) {
if (!scs[i] || !scs[i]->needs_icc)
continue;
scs[i]->icc_path = devm_of_icc_get_by_index(dev, scs[i]->icc_path_index);
if (IS_ERR(scs[i]->icc_path)) {
ret = PTR_ERR(scs[i]->icc_path);
if (ret != -ENODEV)
return ret;
scs[i]->icc_path = NULL;
}
}
for (i = 0; i < num; i++) {
if (!scs[i] || !scs[i]->supply)
continue;

5
drivers/clk/qcom/gdsc.h
View File

@@ -9,6 +9,7 @@
#include <linux/err.h>
#include <linux/pm_domain.h>
struct icc_path;
struct regmap;
struct regulator;
struct reset_controller_dev;
@@ -74,6 +75,10 @@ struct gdsc {
const char *supply;
struct regulator *rsupply;
bool needs_icc;
unsigned int icc_path_index;
struct icc_path *icc_path;
};
struct gdsc_desc {

4
drivers/clk/qcom/gpucc-sm8750.c
View File

@@ -421,7 +421,7 @@ static struct clk_alpha_pll *gpu_cc_alpha_plls[] = {
&gpu_cc_pll0,
};
static u32 gpu_cc_sm8750_critical_cbcrs[] = {
static const u32 gpu_cc_sm8750_critical_cbcrs[] = {
0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
0x9008, /* GPU_CC_CXO_AON_CLK */
0x9064, /* GPU_CC_GX_AHB_FF_CLK */
@@ -430,7 +430,7 @@ static u32 gpu_cc_sm8750_critical_cbcrs[] = {
0x93a8, /* GPU_CC_RSCC_HUB_AON_CLK */
};
static struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
static const struct qcom_cc_driver_data gpu_cc_sm8750_driver_data = {
.alpha_plls = gpu_cc_alpha_plls,
.num_alpha_plls = ARRAY_SIZE(gpu_cc_alpha_plls),
.clk_cbcrs = gpu_cc_sm8750_critical_cbcrs,

1
drivers/clk/qcom/gxclkctl-kaanapali.c
View File

@@ -53,6 +53,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc = {
static const struct of_device_id gx_clkctl_kaanapali_match_table[] = {
{ .compatible = "qcom,glymur-gxclkctl" },
{ .compatible = "qcom,kaanapali-gxclkctl" },
{ .compatible = "qcom,milos-gxclkctl" },
{ .compatible = "qcom,sm8750-gxclkctl" },
{ }
};

30
drivers/clk/qcom/ipq-cmn-pll.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/*
@@ -20,6 +20,11 @@
* and an output clock to NSS (network subsystem) at 300 MHZ. The other output
* clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
*
* On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to
* the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200
* MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS
* are the same as those in the IPQ9574 SoC.
*
* +---------+
* | GCC |
* +--+---+--+
@@ -51,6 +56,7 @@
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq6018-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h>
@@ -131,6 +137,16 @@ static const struct cmn_pll_fixed_output_clk ipq8074_output_clks[] = {
{ /* Sentinel */ }
};
static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = {
CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL),
CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
{ /* Sentinel */ }
};
static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
@@ -199,7 +215,7 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
u32 val, factor;
u32 val, factor, ref_div;
/*
* The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
@@ -207,8 +223,15 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
*/
regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
if (WARN_ON(factor == 0))
factor = 1;
return parent_rate * 2 * factor;
regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val);
ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val);
if (WARN_ON(ref_div == 0))
ref_div = 1;
return div_u64((u64)parent_rate * 2 * factor, ref_div);
}
static int clk_cmn_pll_determine_rate(struct clk_hw *hw,
@@ -461,6 +484,7 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = {
static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
{ .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
{ .compatible = "qcom,ipq5332-cmn-pll", .data = &ipq5332_output_clks },
{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
{ .compatible = "qcom,ipq6018-cmn-pll", .data = &ipq6018_output_clks },
{ .compatible = "qcom,ipq8074-cmn-pll", .data = &ipq8074_output_clks },

3
drivers/clk/qcom/negcc-nord.c
View File

@@ -1918,6 +1918,7 @@ static const struct qcom_reset_map ne_gcc_nord_resets[] = {
[NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 },
[NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 },
[NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 },
[NE_GCC_QUSB2PHY_PRIM_BCR] = { 0x2e000 },
};
static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = {
@@ -1945,7 +1946,7 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
}
static struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
.dfs_rcgs = ne_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
.clk_regs_configure = clk_nord_regs_configure,

4
drivers/clk/qcom/nwgcc-nord.c
View File

@@ -626,7 +626,7 @@ static const struct qcom_reset_map nw_gcc_nord_resets[] = {
[NW_GCC_VIDEO_BCR] = { 0x1a000 },
};
static u32 nw_gcc_nord_critical_cbcrs[] = {
static const u32 nw_gcc_nord_critical_cbcrs[] = {
0x16004, /* NW_GCC_CAMERA_AHB_CLK */
0x16030, /* NW_GCC_CAMERA_XO_CLK */
0x18004, /* NW_GCC_DISP_0_AHB_CLK */
@@ -641,7 +641,7 @@ static u32 nw_gcc_nord_critical_cbcrs[] = {
0x1a044, /* NW_GCC_VIDEO_XO_CLK */
};
static struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
static const struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
.clk_cbcrs = nw_gcc_nord_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs),
};

2
drivers/clk/qcom/segcc-nord.c
View File

@@ -1568,7 +1568,7 @@ static const struct regmap_config se_gcc_nord_regmap_config = {
.fast_io = true,
};
static struct qcom_cc_driver_data se_gcc_nord_driver_data = {
static const struct qcom_cc_driver_data se_gcc_nord_driver_data = {
.dfs_rcgs = se_gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks),
};

158
drivers/clk/qcom/tcsrcc-hawi.c Normal file
View File

@@ -0,0 +1,158 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,hawi-tcsrcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "reset.h"
enum {
DT_BI_TCXO_PAD,
};
static struct clk_branch tcsr_pcie_0_clkref_en = {
.halt_reg = 0x4c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x4c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_0_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_pcie_1_clkref_en = {
.halt_reg = 0x0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_pcie_1_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_ufs_clkref_en = {
.halt_reg = 0x10,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_ufs_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb2_clkref_en = {
.halt_reg = 0x18,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x18,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb2_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch tcsr_usb3_clkref_en = {
.halt_reg = 0x8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "tcsr_usb3_clkref_en",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO_PAD,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *tcsr_cc_hawi_clocks[] = {
[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
};
static const struct regmap_config tcsr_cc_hawi_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x4c,
.fast_io = true,
};
static const struct qcom_cc_desc tcsr_cc_hawi_desc = {
.config = &tcsr_cc_hawi_regmap_config,
.clks = tcsr_cc_hawi_clocks,
.num_clks = ARRAY_SIZE(tcsr_cc_hawi_clocks),
};
static const struct of_device_id tcsr_cc_hawi_match_table[] = {
{ .compatible = "qcom,hawi-tcsrcc" },
{ }
};
MODULE_DEVICE_TABLE(of, tcsr_cc_hawi_match_table);
static int tcsr_cc_hawi_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &tcsr_cc_hawi_desc);
}
static struct platform_driver tcsr_cc_hawi_driver = {
.probe = tcsr_cc_hawi_probe,
.driver = {
.name = "tcsrcc-hawi",
.of_match_table = tcsr_cc_hawi_match_table,
},
};
module_platform_driver(tcsr_cc_hawi_driver);
MODULE_DESCRIPTION("QTI TCSRCC HAWI Driver");
MODULE_LICENSE("GPL");

585
drivers/clk/qcom/videocc-x1p42100.c Normal file
View File

@@ -0,0 +1,585 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,x1p42100-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
};
enum {
P_BI_TCXO,
P_VIDEO_CC_PLL0_OUT_MAIN,
P_VIDEO_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
/* 420.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll0_config = {
.l = 0x15,
.alpha = 0xe000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll video_cc_pll0 = {
.offset = 0x0,
.config = &video_cc_pll0_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1050.0 MHz Configuration */
static const struct alpha_pll_config video_cc_pll1_config = {
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll video_cc_pll1 = {
.offset = 0x1000,
.config = &video_cc_pll1_config,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_mvs0_bse_clk_src[] = {
F(420000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(670000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(848000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(920000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_bse_clk_src = {
.cmd_rcgr = 0x8154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_bse_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_bse_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(210000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(300000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(335000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(424000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(460000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x810c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_bse_div4_div_clk_src = {
.reg = 0x817c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_bse_div4_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_bse_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
.reg = 0x80ec,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0x809c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch video_cc_mvs0_bse_clk = {
.halt_reg = 0x8170,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8170,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_bse_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_bse_div4_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0x80b8,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80b8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x8128,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x812c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x812c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x80e0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_shift_clk = {
.halt_reg = 0x8130,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_shift_clk = {
.halt_reg = 0x8134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_gdsc = {
.gdscr = 0x80a4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0c_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs1c_gdsc = {
.gdscr = 0x8078,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs1c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs1_gdsc = {
.gdscr = 0x80cc,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "video_cc_mvs1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs1c_gdsc.pd,
.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *video_cc_x1p42100_clocks[] = {
[VIDEO_CC_MVS0_BSE_CLK] = &video_cc_mvs0_bse_clk.clkr,
[VIDEO_CC_MVS0_BSE_CLK_SRC] = &video_cc_mvs0_bse_clk_src.clkr,
[VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC] = &video_cc_mvs0_bse_div4_div_clk_src.clkr,
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr,
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
};
static struct gdsc *video_cc_x1p42100_gdscs[] = {
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
};
static const struct qcom_reset_map video_cc_x1p42100_resets[] = {
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0_BSE_BCR] = { 0x816c },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
[VIDEO_CC_XO_CLK_ARES] = { 0x8124, 2 },
};
static struct clk_alpha_pll *video_cc_x1p42100_plls[] = {
&video_cc_pll0,
&video_cc_pll1,
};
static u32 video_cc_x1p42100_critical_cbcrs[] = {
0x80f4, /* VIDEO_CC_AHB_CLK */
0x8150, /* VIDEO_CC_SLEEP_CLK */
0x8124, /* VIDEO_CC_XO_CLK */
};
static const struct regmap_config video_cc_x1p42100_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9f54,
.fast_io = true,
};
static struct qcom_cc_driver_data video_cc_x1p42100_driver_data = {
.alpha_plls = video_cc_x1p42100_plls,
.num_alpha_plls = ARRAY_SIZE(video_cc_x1p42100_plls),
.clk_cbcrs = video_cc_x1p42100_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(video_cc_x1p42100_critical_cbcrs),
};
static const struct qcom_cc_desc video_cc_x1p42100_desc = {
.config = &video_cc_x1p42100_regmap_config,
.clks = video_cc_x1p42100_clocks,
.num_clks = ARRAY_SIZE(video_cc_x1p42100_clocks),
.resets = video_cc_x1p42100_resets,
.num_resets = ARRAY_SIZE(video_cc_x1p42100_resets),
.gdscs = video_cc_x1p42100_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_x1p42100_gdscs),
.use_rpm = true,
.driver_data = &video_cc_x1p42100_driver_data,
};
static const struct of_device_id video_cc_x1p42100_match_table[] = {
{ .compatible = "qcom,x1p42100-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_x1p42100_match_table);
static int video_cc_x1p42100_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &video_cc_x1p42100_desc);
}
static struct platform_driver video_cc_x1p42100_driver = {
.probe = video_cc_x1p42100_probe,
.driver = {
.name = "videocc-x1p42100",
.of_match_table = video_cc_x1p42100_match_table,
},
};
module_platform_driver(video_cc_x1p42100_driver);
MODULE_DESCRIPTION("QTI VIDEOCC X1P42100 Driver");
MODULE_LICENSE("GPL");

20
drivers/interconnect/core.c
View File

@@ -443,6 +443,26 @@ struct icc_path *devm_of_icc_get(struct device *dev, const char *name)
}
EXPORT_SYMBOL_GPL(devm_of_icc_get);
struct icc_path *devm_of_icc_get_by_index(struct device *dev, int idx)
{
struct icc_path **ptr, *path;
ptr = devres_alloc(devm_icc_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
path = of_icc_get_by_index(dev, idx);
if (!IS_ERR(path)) {
*ptr = path;
devres_add(dev, ptr);
} else {
devres_free(ptr);
}
return path;
}
EXPORT_SYMBOL_GPL(devm_of_icc_get_by_index);
/**
* of_icc_get_by_index() - get a path handle from a DT node based on index
* @dev: device pointer for the consumer device

253
include/dt-bindings/clock/qcom,hawi-gcc.h Normal file
View File

@@ -0,0 +1,253 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_HAWI_H
#define _DT_BINDINGS_CLK_QCOM_GCC_HAWI_H
/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
#define GCC_AGGRE_STARDUSTNOC_USB3_PRIM_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
#define GCC_BOOT_ROM_AHB_CLK 3
#define GCC_CAM_BIST_MCLK_AHB_CLK 4
#define GCC_CAMERA_AHB_CLK 5
#define GCC_CAMERA_HF_AXI_CLK 6
#define GCC_CAMERA_RSC_CORE_CLK 7
#define GCC_CAMERA_SF_AXI_CLK 8
#define GCC_CAMERA_XO_CLK 9
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11
#define GCC_CNOC_PCIE_SF_AXI_CLK 12
#define GCC_EVA_AHB_CLK 13
#define GCC_EVA_AXI0_CLK 14
#define GCC_EVA_AXI0C_CLK 15
#define GCC_EVA_XO_CLK 16
#define GCC_GP1_CLK 17
#define GCC_GP1_CLK_SRC 18
#define GCC_GP2_CLK 19
#define GCC_GP2_CLK_SRC 20
#define GCC_GP3_CLK 21
#define GCC_GP3_CLK_SRC 22
#define GCC_GPLL0 23
#define GCC_GPLL0_OUT_EVEN 24
#define GCC_GPLL4 25
#define GCC_GPLL5 26
#define GCC_GPLL7 27
#define GCC_GPLL9 28
#define GCC_GPU_CFG_AHB_CLK 29
#define GCC_GPU_GEMNOC_GFX_CLK 30
#define GCC_GPU_GPLL0_CLK_SRC 31
#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
#define GCC_GPU_RSC_CORE_CLK 33
#define GCC_GPU_SMMU_VOTE_CLK 34
#define GCC_MMU_TCU_VOTE_CLK 35
#define GCC_PCIE_0_AUX_CLK 36
#define GCC_PCIE_0_AUX_CLK_SRC 37
#define GCC_PCIE_0_CFG_AHB_CLK 38
#define GCC_PCIE_0_MSTR_AXI_CLK 39
#define GCC_PCIE_0_PHY_AUX_CLK 40
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 41
#define GCC_PCIE_0_PHY_RCHNG_CLK 42
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 43
#define GCC_PCIE_0_PIPE_CLK 44
#define GCC_PCIE_0_PIPE_CLK_SRC 45
#define GCC_PCIE_0_PIPE_DIV2_CLK 46
#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 47
#define GCC_PCIE_0_SLV_AXI_CLK 48
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
#define GCC_PCIE_1_AUX_CLK 50
#define GCC_PCIE_1_AUX_CLK_SRC 51
#define GCC_PCIE_1_CFG_AHB_CLK 52
#define GCC_PCIE_1_MSTR_AXI_CLK 53
#define GCC_PCIE_1_PHY_AUX_CLK 54
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 55
#define GCC_PCIE_1_PHY_RCHNG_CLK 56
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 57
#define GCC_PCIE_1_PIPE_CLK 58
#define GCC_PCIE_1_PIPE_CLK_SRC 59
#define GCC_PCIE_1_PIPE_DIV2_CLK 60
#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 61
#define GCC_PCIE_1_RSC_CORE_CLK 62
#define GCC_PCIE_1_SLV_AXI_CLK 63
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 64
#define GCC_PCIE_RSC_CORE_CLK 65
#define GCC_PCIE_RSCC_CFG_AHB_CLK 66
#define GCC_PCIE_RSCC_XO_CLK 67
#define GCC_PDM2_CLK 68
#define GCC_PDM2_CLK_SRC 69
#define GCC_PDM_AHB_CLK 70
#define GCC_PDM_XO4_CLK 71
#define GCC_QUPV3_I2C_CORE_CLK 72
#define GCC_QUPV3_I2C_S0_CLK 73
#define GCC_QUPV3_I2C_S0_CLK_SRC 74
#define GCC_QUPV3_I2C_S1_CLK 75
#define GCC_QUPV3_I2C_S1_CLK_SRC 76
#define GCC_QUPV3_I2C_S2_CLK 77
#define GCC_QUPV3_I2C_S2_CLK_SRC 78
#define GCC_QUPV3_I2C_S3_CLK 79
#define GCC_QUPV3_I2C_S3_CLK_SRC 80
#define GCC_QUPV3_I2C_S4_CLK 81
#define GCC_QUPV3_I2C_S4_CLK_SRC 82
#define GCC_QUPV3_I2C_S_AHB_CLK 83
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84
#define GCC_QUPV3_WRAP1_CORE_CLK 85
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 86
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S0_CLK 88
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S1_CLK 90
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
#define GCC_QUPV3_WRAP1_S2_CLK 92
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
#define GCC_QUPV3_WRAP1_S3_CLK 94
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
#define GCC_QUPV3_WRAP1_S4_CLK 96
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S5_CLK 98
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
#define GCC_QUPV3_WRAP1_S6_CLK 100
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
#define GCC_QUPV3_WRAP1_S7_CLK 102
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 104
#define GCC_QUPV3_WRAP2_CORE_CLK 105
#define GCC_QUPV3_WRAP2_S0_CLK 106
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 107
#define GCC_QUPV3_WRAP2_S1_CLK 108
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 109
#define GCC_QUPV3_WRAP2_S2_CLK 110
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 111
#define GCC_QUPV3_WRAP2_S3_CLK 112
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 113
#define GCC_QUPV3_WRAP2_S4_CLK 114
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 115
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 116
#define GCC_QUPV3_WRAP3_CORE_CLK 117
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 118
#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 119
#define GCC_QUPV3_WRAP3_S0_CLK 120
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 121
#define GCC_QUPV3_WRAP3_S1_CLK 122
#define GCC_QUPV3_WRAP3_S1_CLK_SRC 123
#define GCC_QUPV3_WRAP3_S2_CLK 124
#define GCC_QUPV3_WRAP3_S2_CLK_SRC 125
#define GCC_QUPV3_WRAP3_S3_CLK 126
#define GCC_QUPV3_WRAP3_S3_CLK_SRC 127
#define GCC_QUPV3_WRAP3_S4_CLK 128
#define GCC_QUPV3_WRAP3_S4_CLK_SRC 129
#define GCC_QUPV3_WRAP3_S5_CLK 130
#define GCC_QUPV3_WRAP3_S5_CLK_SRC 131
#define GCC_QUPV3_WRAP4_CORE_2X_CLK 132
#define GCC_QUPV3_WRAP4_CORE_CLK 133
#define GCC_QUPV3_WRAP4_S0_CLK 134
#define GCC_QUPV3_WRAP4_S0_CLK_SRC 135
#define GCC_QUPV3_WRAP4_S1_CLK 136
#define GCC_QUPV3_WRAP4_S1_CLK_SRC 137
#define GCC_QUPV3_WRAP4_S2_CLK 138
#define GCC_QUPV3_WRAP4_S2_CLK_SRC 139
#define GCC_QUPV3_WRAP4_S3_CLK 140
#define GCC_QUPV3_WRAP4_S3_CLK_SRC 141
#define GCC_QUPV3_WRAP4_S4_CLK 142
#define GCC_QUPV3_WRAP4_S4_CLK_SRC 143
#define GCC_QUPV3_WRAP_1_M_AXI_CLK 144
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 145
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 146
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 147
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 148
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 149
#define GCC_QUPV3_WRAP_4_M_AHB_CLK 150
#define GCC_QUPV3_WRAP_4_S_AHB_CLK 151
#define GCC_SDCC2_AHB_CLK 152
#define GCC_SDCC2_APPS_CLK 153
#define GCC_SDCC2_APPS_CLK_SRC 154
#define GCC_SDCC4_AHB_CLK 155
#define GCC_SDCC4_APPS_CLK 156
#define GCC_SDCC4_APPS_CLK_SRC 157
#define GCC_UFS_PHY_AHB_CLK 158
#define GCC_UFS_PHY_AXI_CLK 159
#define GCC_UFS_PHY_AXI_CLK_SRC 160
#define GCC_UFS_PHY_ICE_CORE_CLK 161
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 162
#define GCC_UFS_PHY_PHY_AUX_CLK 163
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 165
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 166
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 168
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 169
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 170
#define GCC_UFS_PHY_UNIPRO_5_CORE_CLK 171
#define GCC_UFS_PHY_UNIPRO_5_CORE_CLK_SRC 172
#define GCC_USB30_PRIM_MASTER_CLK 173
#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
#define GCC_USB30_PRIM_SLEEP_CLK 178
#define GCC_USB3_PRIM_PHY_AUX_CLK 179
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
#define GCC_VIDEO_AHB_CLK 184
#define GCC_VIDEO_AXI0_CLK 185
#define GCC_VIDEO_AXI0C_CLK 186
#define GCC_VIDEO_XO_CLK 187
/* GCC power domains */
#define GCC_PCIE_0_GDSC 0
#define GCC_PCIE_0_PHY_GDSC 1
#define GCC_PCIE_1_GDSC 2
#define GCC_PCIE_1_PHY_GDSC 3
#define GCC_UFS_MEM_PHY_GDSC 4
#define GCC_UFS_PHY_GDSC 5
#define GCC_USB30_PRIM_GDSC 6
#define GCC_USB3_PHY_GDSC 7
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_EVA_AXI0_CLK_ARES 1
#define GCC_EVA_AXI0C_CLK_ARES 2
#define GCC_EVA_BCR 3
#define GCC_GPU_BCR 4
#define GCC_PCIE_0_BCR 5
#define GCC_PCIE_0_LINK_DOWN_BCR 6
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_0_PHY_BCR 8
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9
#define GCC_PCIE_1_BCR 10
#define GCC_PCIE_1_LINK_DOWN_BCR 11
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_1_PHY_BCR 13
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14
#define GCC_PCIE_PHY_BCR 15
#define GCC_PCIE_PHY_CFG_AHB_BCR 16
#define GCC_PCIE_PHY_COM_BCR 17
#define GCC_PCIE_RSCC_BCR 18
#define GCC_PDM_BCR 19
#define GCC_QUPV3_WRAPPER_1_BCR 20
#define GCC_QUPV3_WRAPPER_2_BCR 21
#define GCC_QUPV3_WRAPPER_3_BCR 22
#define GCC_QUPV3_WRAPPER_4_BCR 23
#define GCC_QUPV3_WRAPPER_I2C_BCR 24
#define GCC_QUSB2PHY_PRIM_BCR 25
#define GCC_QUSB2PHY_SEC_BCR 26
#define GCC_SDCC2_BCR 27
#define GCC_SDCC4_BCR 28
#define GCC_TCSR_PCIE_BCR 29
#define GCC_UFS_PHY_BCR 30
#define GCC_USB30_PRIM_BCR 31
#define GCC_USB3_DP_PHY_PRIM_BCR 32
#define GCC_USB3_DP_PHY_SEC_BCR 33
#define GCC_USB3_PHY_PRIM_BCR 34
#define GCC_USB3_PHY_SEC_BCR 35
#define GCC_USB3PHY_PHY_PRIM_BCR 36
#define GCC_USB3PHY_PHY_SEC_BCR 37
#define GCC_VIDEO_AXI0_CLK_ARES 38
#define GCC_VIDEO_AXI0C_CLK_ARES 39
#define GCC_VIDEO_BCR 40
#define GCC_VIDEO_XO_CLK_ARES 41
#endif

16
include/dt-bindings/clock/qcom,hawi-tcsrcc.h Normal file
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@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_HAWI_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_HAWI_H
/* TCSR_CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_PCIE_1_CLKREF_EN 1
#define TCSR_UFS_CLKREF_EN 2
#define TCSR_USB2_CLKREF_EN 3
#define TCSR_USB3_CLKREF_EN 4
#endif

19
include/dt-bindings/clock/qcom,ipq5332-cmn-pll.h Normal file
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
#define _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
/* CMN PLL core clock. */
#define IPQ5332_CMN_PLL_CLK 0
/* The output clocks from CMN PLL of IPQ5332. */
#define IPQ5332_XO_24MHZ_CLK 1
#define IPQ5332_SLEEP_32KHZ_CLK 2
#define IPQ5332_PCS_31P25MHZ_CLK 3
#define IPQ5332_NSS_300MHZ_CLK 4
#define IPQ5332_PPE_200MHZ_CLK 5
#define IPQ5332_ETH_50MHZ_CLK 6
#endif

172
include/dt-bindings/clock/qcom,ipq9650-gcc.h Normal file
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@@ -0,0 +1,172 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H
#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H
#define GCC_ADSS_PWM_CLK 0
#define GCC_ADSS_PWM_CLK_SRC 1
#define GCC_ANOC_PCIE0_1LANE_M_CLK 2
#define GCC_ANOC_PCIE0_1LANE_S_CLK 3
#define GCC_ANOC_PCIE1_2LANE_M_CLK 4
#define GCC_ANOC_PCIE1_2LANE_S_CLK 5
#define GCC_ANOC_PCIE2_2LANE_M_CLK 6
#define GCC_ANOC_PCIE2_2LANE_S_CLK 7
#define GCC_ANOC_PCIE3_2LANE_M_CLK 8
#define GCC_ANOC_PCIE3_2LANE_S_CLK 9
#define GCC_ANOC_PCIE4_1LANE_M_CLK 10
#define GCC_ANOC_PCIE4_1LANE_S_CLK 11
#define GCC_CMN_12GPLL_AHB_CLK 12
#define GCC_CMN_12GPLL_APU_CLK 13
#define GCC_CMN_12GPLL_SYS_CLK 14
#define GCC_CMN_LDO_CLK 15
#define GCC_MDIO_AHB_CLK 16
#define GCC_NSSCC_CLK 17
#define GCC_NSSCFG_CLK 18
#define GCC_NSSNOC_ATB_CLK 19
#define GCC_NSSNOC_MEMNOC_1_CLK 20
#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21
#define GCC_NSSNOC_MEMNOC_CLK 22
#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23
#define GCC_NSSNOC_NSSCC_CLK 24
#define GCC_NSSNOC_PCNOC_1_CLK 25
#define GCC_NSSNOC_QOSGEN_REF_CLK 26
#define GCC_NSSNOC_SNOC_1_CLK 27
#define GCC_NSSNOC_SNOC_CLK 28
#define GCC_NSSNOC_TIMEOUT_REF_CLK 29
#define GCC_NSSNOC_XO_DCD_CLK 30
#define GCC_NSS_TS_CLK 31
#define GCC_NSS_TS_CLK_SRC 32
#define GCC_PCIE0_AHB_CLK 33
#define GCC_PCIE0_AUX_CLK 34
#define GCC_PCIE0_AXI_M_CLK 35
#define GCC_PCIE0_AXI_M_CLK_SRC 36
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37
#define GCC_PCIE0_AXI_S_CLK 38
#define GCC_PCIE0_AXI_S_CLK_SRC 39
#define GCC_PCIE0_PIPE_CLK 40
#define GCC_PCIE0_PIPE_CLK_SRC 41
#define GCC_PCIE0_RCHNG_CLK 42
#define GCC_PCIE0_RCHNG_CLK_SRC 43
#define GCC_PCIE1_AHB_CLK 44
#define GCC_PCIE1_AUX_CLK 45
#define GCC_PCIE1_AXI_M_CLK 46
#define GCC_PCIE1_AXI_M_CLK_SRC 47
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48
#define GCC_PCIE1_AXI_S_CLK 49
#define GCC_PCIE1_AXI_S_CLK_SRC 50
#define GCC_PCIE1_PIPE_CLK 51
#define GCC_PCIE1_PIPE_CLK_SRC 52
#define GCC_PCIE1_RCHNG_CLK 53
#define GCC_PCIE1_RCHNG_CLK_SRC 54
#define GCC_PCIE2_AHB_CLK 55
#define GCC_PCIE2_AUX_CLK 56
#define GCC_PCIE2_AXI_M_CLK 57
#define GCC_PCIE2_AXI_M_CLK_SRC 58
#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59
#define GCC_PCIE2_AXI_S_CLK 60
#define GCC_PCIE2_AXI_S_CLK_SRC 61
#define GCC_PCIE2_PIPE_CLK 62
#define GCC_PCIE2_PIPE_CLK_SRC 63
#define GCC_PCIE2_RCHNG_CLK 64
#define GCC_PCIE2_RCHNG_CLK_SRC 65
#define GCC_PCIE3_AHB_CLK 66
#define GCC_PCIE3_AUX_CLK 67
#define GCC_PCIE3_AXI_M_CLK 68
#define GCC_PCIE3_AXI_M_CLK_SRC 69
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70
#define GCC_PCIE3_AXI_S_CLK 71
#define GCC_PCIE3_AXI_S_CLK_SRC 72
#define GCC_PCIE3_PIPE_CLK 73
#define GCC_PCIE3_PIPE_CLK_SRC 74
#define GCC_PCIE3_RCHNG_CLK 75
#define GCC_PCIE3_RCHNG_CLK_SRC 76
#define GCC_PCIE4_AHB_CLK 77
#define GCC_PCIE4_AUX_CLK 78
#define GCC_PCIE4_AXI_M_CLK 79
#define GCC_PCIE4_AXI_M_CLK_SRC 80
#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81
#define GCC_PCIE4_AXI_S_CLK 82
#define GCC_PCIE4_AXI_S_CLK_SRC 83
#define GCC_PCIE4_PIPE_CLK 84
#define GCC_PCIE4_PIPE_CLK_SRC 85
#define GCC_PCIE4_RCHNG_CLK 86
#define GCC_PCIE4_RCHNG_CLK_SRC 87
#define GCC_PCIE_AUX_CLK_SRC 88
#define GCC_PCNOC_BFDCD_CLK_SRC 89
#define GCC_QDSS_AT_CLK 90
#define GCC_QDSS_AT_CLK_SRC 91
#define GCC_QDSS_DAP_CLK 92
#define GCC_QDSS_TSCTR_CLK_SRC 93
#define GCC_QPIC_AHB_CLK 94
#define GCC_QPIC_CLK 95
#define GCC_QPIC_CLK_SRC 96
#define GCC_QPIC_IO_MACRO_CLK 97
#define GCC_QPIC_IO_MACRO_CLK_SRC 98
#define GCC_QPIC_SLEEP_CLK 99
#define GCC_QUPV3_2X_CORE_CLK 100
#define GCC_QUPV3_2X_CORE_CLK_SRC 101
#define GCC_QUPV3_AHB_MST_CLK 102
#define GCC_QUPV3_AHB_SLV_CLK 103
#define GCC_QUPV3_CORE_CLK 104
#define GCC_QUPV3_SLEEP_CLK 105
#define GCC_QUPV3_WRAP_SE0_CLK 106
#define GCC_QUPV3_WRAP_SE0_CLK_SRC 107
#define GCC_QUPV3_WRAP_SE1_CLK 108
#define GCC_QUPV3_WRAP_SE1_CLK_SRC 109
#define GCC_QUPV3_WRAP_SE2_CLK 110
#define GCC_QUPV3_WRAP_SE2_CLK_SRC 111
#define GCC_QUPV3_WRAP_SE3_CLK 112
#define GCC_QUPV3_WRAP_SE3_CLK_SRC 113
#define GCC_QUPV3_WRAP_SE4_CLK 114
#define GCC_QUPV3_WRAP_SE4_CLK_SRC 115
#define GCC_QUPV3_WRAP_SE5_CLK 116
#define GCC_QUPV3_WRAP_SE5_CLK_SRC 117
#define GCC_QUPV3_WRAP_SE6_CLK 118
#define GCC_QUPV3_WRAP_SE6_CLK_SRC 119
#define GCC_QUPV3_WRAP_SE7_CLK 120
#define GCC_QUPV3_WRAP_SE7_CLK_SRC 121
#define GCC_SDCC1_AHB_CLK 122
#define GCC_SDCC1_APPS_CLK 123
#define GCC_SDCC1_APPS_CLK_SRC 124
#define GCC_SDCC1_ICE_CORE_CLK 125
#define GCC_SDCC1_ICE_CORE_CLK_SRC 126
#define GCC_SLEEP_CLK_SRC 127
#define GCC_SNOC_USB_CLK 128
#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
#define GCC_TLMM_AHB_CLK 130
#define GCC_TLMM_CLK 131
#define GCC_UNIPHY0_AHB_CLK 132
#define GCC_UNIPHY0_SYS_CLK 133
#define GCC_UNIPHY1_AHB_CLK 134
#define GCC_UNIPHY1_SYS_CLK 135
#define GCC_UNIPHY2_AHB_CLK 136
#define GCC_UNIPHY2_SYS_CLK 137
#define GCC_UNIPHY_SYS_CLK_SRC 138
#define GCC_USB0_AUX_CLK 139
#define GCC_USB0_AUX_CLK_SRC 140
#define GCC_USB0_EUD_AT_CLK 141
#define GCC_USB0_MASTER_CLK 142
#define GCC_USB0_MASTER_CLK_SRC 143
#define GCC_USB0_MOCK_UTMI_CLK 144
#define GCC_USB0_MOCK_UTMI_CLK_SRC 145
#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146
#define GCC_USB0_PHY_CFG_AHB_CLK 147
#define GCC_USB0_PIPE_CLK 148
#define GCC_USB0_PIPE_CLK_SRC 149
#define GCC_USB0_SLEEP_CLK 150
#define GCC_USB1_MASTER_CLK 151
#define GCC_USB1_MOCK_UTMI_CLK 152
#define GCC_USB1_MOCK_UTMI_CLK_SRC 153
#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154
#define GCC_USB1_PHY_CFG_AHB_CLK 155
#define GCC_USB1_SLEEP_CLK 156
#define GCC_XO_CLK_SRC 157
#define GPLL0 158
#define GPLL0_MAIN 159
#define GPLL2 160
#define GPLL2_OUT_MAIN 161
#define GPLL4 162
#endif

1
include/dt-bindings/clock/qcom,nord-negcc.h
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@@ -120,5 +120,6 @@
#define NE_GCC_USB3_PHY_SEC_BCR 10
#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
#define NE_GCC_QUSB2PHY_PRIM_BCR 13
#endif

2
include/dt-bindings/clock/qcom,rpmh.h
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@@ -33,5 +33,7 @@
#define RPMH_HWKM_CLK 24
#define RPMH_QLINK_CLK 25
#define RPMH_QLINK_CLK_A 26
#define RPMH_LN_BB_CLK4 27
#define RPMH_LN_BB_CLK4_A 28
#endif

3
include/dt-bindings/clock/qcom,x1e80100-camcc.h
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@@ -115,6 +115,9 @@
#define CAM_CC_SLEEP_CLK_SRC 105
#define CAM_CC_SLOW_AHB_CLK_SRC 106
#define CAM_CC_XO_CLK_SRC 107
#define CAM_CC_QDSS_DEBUG_CLK 108
#define CAM_CC_QDSS_DEBUG_CLK_SRC 109
#define CAM_CC_QDSS_DEBUG_XO_CLK 110
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0

48
include/dt-bindings/clock/qcom,x1p42100-videocc.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H
/* VIDEO_CC clocks */
#define VIDEO_CC_MVS0_CLK 0
#define VIDEO_CC_MVS0_CLK_SRC 1
#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
#define VIDEO_CC_MVS0C_CLK 3
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
#define VIDEO_CC_MVS1_CLK 5
#define VIDEO_CC_MVS1_CLK_SRC 6
#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
#define VIDEO_CC_MVS1C_CLK 8
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
#define VIDEO_CC_PLL0 10
#define VIDEO_CC_PLL1 11
#define VIDEO_CC_MVS0_SHIFT_CLK 12
#define VIDEO_CC_MVS0C_SHIFT_CLK 13
#define VIDEO_CC_MVS1_SHIFT_CLK 14
#define VIDEO_CC_MVS1C_SHIFT_CLK 15
#define VIDEO_CC_XO_CLK_SRC 16
#define VIDEO_CC_MVS0_BSE_CLK 17
#define VIDEO_CC_MVS0_BSE_CLK_SRC 18
#define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0C_GDSC 0
#define VIDEO_CC_MVS0_GDSC 1
#define VIDEO_CC_MVS1C_GDSC 2
#define VIDEO_CC_MVS1_GDSC 3
/* VIDEO_CC resets */
#define CVP_VIDEO_CC_INTERFACE_BCR 0
#define CVP_VIDEO_CC_MVS0_BCR 1
#define CVP_VIDEO_CC_MVS0C_BCR 2
#define CVP_VIDEO_CC_MVS1_BCR 3
#define CVP_VIDEO_CC_MVS1C_BCR 4
#define VIDEO_CC_MVS0C_CLK_ARES 5
#define VIDEO_CC_MVS1C_CLK_ARES 6
#define VIDEO_CC_XO_CLK_ARES 7
#define VIDEO_CC_MVS0_BSE_BCR 8
#endif

215
include/dt-bindings/reset/qcom,ipq9650-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
#define GCC_ADSS_BCR 0
#define GCC_ADSS_PWM_CLK_ARES 1
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3
#define GCC_APSS_AHB_CLK_ARES 4
#define GCC_APSS_ATB_CLK_ARES 5
#define GCC_APSS_AXI_CLK_ARES 6
#define GCC_APSS_TS_CLK_ARES 7
#define GCC_BOOT_ROM_AHB_CLK_ARES 8
#define GCC_BOOT_ROM_BCR 9
#define GCC_CMN_12GPLL_AHB_CLK_ARES 10
#define GCC_CMN_12GPLL_APU_CLK_ARES 11
#define GCC_CMN_12GPLL_SYS_CLK_ARES 12
#define GCC_CMN_BLK_BCR 13
#define GCC_CMN_LDO_CLK_ARES 14
#define GCC_CPUSS_TRIG_CLK_ARES 15
#define GCC_GP1_CLK_ARES 16
#define GCC_GP2_CLK_ARES 17
#define GCC_GP3_CLK_ARES 18
#define GCC_MDIO_AHB_CLK_ARES 19
#define GCC_MDIO_BCR 20
#define GCC_NSSCC_CLK_ARES 21
#define GCC_NSSCFG_CLK_ARES 22
#define GCC_NSSNOC_ATB_CLK_ARES 23
#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24
#define GCC_NSSNOC_MEMNOC_CLK_ARES 25
#define GCC_NSSNOC_NSSCC_CLK_ARES 26
#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27
#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28
#define GCC_NSSNOC_SNOC_1_CLK_ARES 29
#define GCC_NSSNOC_SNOC_CLK_ARES 30
#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31
#define GCC_NSSNOC_XO_DCD_CLK_ARES 32
#define GCC_NSS_BCR 33
#define GCC_NSS_TS_CLK_ARES 34
#define GCC_PCIE0PHY_PHY_BCR 35
#define GCC_PCIE0_AHB_CLK_ARES 36
#define GCC_PCIE0_AHB_RESET 37
#define GCC_PCIE0_AUX_CLK_ARES 38
#define GCC_PCIE0_AUX_RESET 39
#define GCC_PCIE0_AXI_M_CLK_ARES 40
#define GCC_PCIE0_AXI_M_RESET 41
#define GCC_PCIE0_AXI_M_STICKY_RESET 42
#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43
#define GCC_PCIE0_AXI_S_CLK_ARES 44
#define GCC_PCIE0_AXI_S_RESET 45
#define GCC_PCIE0_AXI_S_STICKY_RESET 46
#define GCC_PCIE0_BCR 47
#define GCC_PCIE0_CORE_STICKY_RESET 48
#define GCC_PCIE0_LINK_DOWN_BCR 49
#define GCC_PCIE0_PHY_BCR 50
#define GCC_PCIE0_PIPE_CLK_ARES 51
#define GCC_PCIE0_PIPE_RESET 52
#define GCC_PCIE1PHY_PHY_BCR 53
#define GCC_PCIE1_AHB_CLK_ARES 54
#define GCC_PCIE1_AHB_RESET 55
#define GCC_PCIE1_AUX_CLK_ARES 56
#define GCC_PCIE1_AUX_RESET 57
#define GCC_PCIE1_AXI_M_CLK_ARES 58
#define GCC_PCIE1_AXI_M_RESET 59
#define GCC_PCIE1_AXI_M_STICKY_RESET 60
#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61
#define GCC_PCIE1_AXI_S_CLK_ARES 62
#define GCC_PCIE1_AXI_S_RESET 63
#define GCC_PCIE1_AXI_S_STICKY_RESET 64
#define GCC_PCIE1_BCR 65
#define GCC_PCIE1_CORE_STICKY_RESET 66
#define GCC_PCIE1_LINK_DOWN_BCR 67
#define GCC_PCIE1_PHY_BCR 68
#define GCC_PCIE1_PIPE_CLK_ARES 69
#define GCC_PCIE1_PIPE_RESET 70
#define GCC_PCIE2PHY_PHY_BCR 71
#define GCC_PCIE2_AHB_CLK_ARES 72
#define GCC_PCIE2_AHB_RESET 73
#define GCC_PCIE2_AUX_CLK_ARES 74
#define GCC_PCIE2_AUX_RESET 75
#define GCC_PCIE2_AXI_M_CLK_ARES 76
#define GCC_PCIE2_AXI_M_RESET 77
#define GCC_PCIE2_AXI_M_STICKY_RESET 78
#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79
#define GCC_PCIE2_AXI_S_CLK_ARES 80
#define GCC_PCIE2_AXI_S_RESET 81
#define GCC_PCIE2_AXI_S_STICKY_RESET 82
#define GCC_PCIE2_BCR 83
#define GCC_PCIE2_CORE_STICKY_RESET 84
#define GCC_PCIE2_LINK_DOWN_BCR 85
#define GCC_PCIE2_PHY_BCR 86
#define GCC_PCIE2_PIPE_CLK_ARES 87
#define GCC_PCIE2_PIPE_RESET 88
#define GCC_PCIE3PHY_PHY_BCR 89
#define GCC_PCIE3_AHB_CLK_ARES 90
#define GCC_PCIE3_AHB_RESET 91
#define GCC_PCIE3_AUX_CLK_ARES 92
#define GCC_PCIE3_AUX_RESET 93
#define GCC_PCIE3_AXI_M_CLK_ARES 94
#define GCC_PCIE3_AXI_M_RESET 95
#define GCC_PCIE3_AXI_M_STICKY_RESET 96
#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97
#define GCC_PCIE3_AXI_S_CLK_ARES 98
#define GCC_PCIE3_AXI_S_RESET 99
#define GCC_PCIE3_AXI_S_STICKY_RESET 100
#define GCC_PCIE3_BCR 101
#define GCC_PCIE3_CORE_STICKY_RESET 102
#define GCC_PCIE3_LINK_DOWN_BCR 103
#define GCC_PCIE3_PHY_BCR 104
#define GCC_PCIE3_PIPE_CLK_ARES 105
#define GCC_PCIE3_PIPE_RESET 106
#define GCC_PCIE4PHY_PHY_BCR 107
#define GCC_PCIE4_AHB_CLK_ARES 108
#define GCC_PCIE4_AHB_RESET 109
#define GCC_PCIE4_AUX_CLK_ARES 110
#define GCC_PCIE4_AUX_RESET 111
#define GCC_PCIE4_AXI_M_CLK_ARES 112
#define GCC_PCIE4_AXI_M_RESET 113
#define GCC_PCIE4_AXI_M_STICKY_RESET 114
#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115
#define GCC_PCIE4_AXI_S_CLK_ARES 116
#define GCC_PCIE4_AXI_S_RESET 117
#define GCC_PCIE4_AXI_S_STICKY_RESET 118
#define GCC_PCIE4_BCR 119
#define GCC_PCIE4_CORE_STICKY_RESET 120
#define GCC_PCIE4_LINK_DOWN_BCR 121
#define GCC_PCIE4_PHY_BCR 122
#define GCC_PCIE4_PIPE_CLK_ARES 123
#define GCC_PCIE4_PIPE_RESET 124
#define GCC_QDSS_APB2JTAG_CLK_ARES 125
#define GCC_QDSS_AT_CLK_ARES 126
#define GCC_QDSS_BCR 127
#define GCC_QDSS_CFG_AHB_CLK_ARES 128
#define GCC_QDSS_DAP_AHB_CLK_ARES 129
#define GCC_QDSS_DAP_CLK_ARES 130
#define GCC_QDSS_ETR_USB_CLK_ARES 131
#define GCC_QDSS_EUD_AT_CLK_ARES 132
#define GCC_QDSS_STM_CLK_ARES 133
#define GCC_QDSS_TRACECLKIN_CLK_ARES 134
#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 135
#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 136
#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 137
#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 138
#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 139
#define GCC_QDSS_TS_CLK_ARES 140
#define GCC_QPIC_AHB_CLK_ARES 141
#define GCC_QPIC_BCR 142
#define GCC_QPIC_CLK_ARES 143
#define GCC_QPIC_IO_MACRO_CLK_ARES 144
#define GCC_QPIC_SLEEP_CLK_ARES 145
#define GCC_QUPV3_2X_CORE_CLK_ARES 146
#define GCC_QUPV3_AHB_MST_CLK_ARES 147
#define GCC_QUPV3_AHB_SLV_CLK_ARES 148
#define GCC_QUPV3_BCR 149
#define GCC_QUPV3_CORE_CLK_ARES 150
#define GCC_QUPV3_WRAP_SE0_BCR 151
#define GCC_QUPV3_WRAP_SE0_CLK_ARES 152
#define GCC_QUPV3_WRAP_SE1_BCR 153
#define GCC_QUPV3_WRAP_SE1_CLK_ARES 154
#define GCC_QUPV3_WRAP_SE2_BCR 155
#define GCC_QUPV3_WRAP_SE2_CLK_ARES 156
#define GCC_QUPV3_WRAP_SE3_BCR 157
#define GCC_QUPV3_WRAP_SE3_CLK_ARES 158
#define GCC_QUPV3_WRAP_SE4_BCR 159
#define GCC_QUPV3_WRAP_SE4_CLK_ARES 160
#define GCC_QUPV3_WRAP_SE5_BCR 161
#define GCC_QUPV3_WRAP_SE5_CLK_ARES 162
#define GCC_QUPV3_WRAP_SE6_BCR 163
#define GCC_QUPV3_WRAP_SE6_CLK_ARES 164
#define GCC_QUPV3_WRAP_SE7_BCR 165
#define GCC_QUPV3_WRAP_SE7_CLK_ARES 166
#define GCC_QUSB2_0_PHY_BCR 167
#define GCC_QUSB2_1_PHY_BCR 168
#define GCC_SDCC1_APPS_CLK_ARES 169
#define GCC_SDCC1_ICE_CORE_CLK_ARES 170
#define GCC_SDCC_BCR 171
#define GCC_TLMM_AHB_CLK_ARES 172
#define GCC_TLMM_BCR 173
#define GCC_TLMM_CLK_ARES 174
#define GCC_UNIPHY0_AHB_CLK_ARES 175
#define GCC_UNIPHY0_BCR 176
#define GCC_UNIPHY0_PMA_BCR 177
#define GCC_UNIPHY0_SYS_CLK_ARES 178
#define GCC_UNIPHY0_XPCS_ARES 179
#define GCC_UNIPHY1_AHB_CLK_ARES 180
#define GCC_UNIPHY1_BCR 181
#define GCC_UNIPHY1_PMA_BCR 182
#define GCC_UNIPHY1_SYS_CLK_ARES 183
#define GCC_UNIPHY1_XPCS_ARES 184
#define GCC_UNIPHY2_AHB_CLK_ARES 185
#define GCC_UNIPHY2_BCR 186
#define GCC_UNIPHY2_PMA_BCR 187
#define GCC_UNIPHY2_SYS_CLK_ARES 188
#define GCC_UNIPHY2_XPCS_ARES 189
#define GCC_USB0_AUX_CLK_ARES 190
#define GCC_USB0_MASTER_CLK_ARES 191
#define GCC_USB0_MOCK_UTMI_CLK_ARES 192
#define GCC_USB0_PHY_BCR 193
#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 194
#define GCC_USB0_PIPE_CLK_ARES 195
#define GCC_USB0_SLEEP_CLK_ARES 196
#define GCC_USB1_BCR 197
#define GCC_USB1_MASTER_CLK_ARES 198
#define GCC_USB1_MOCK_UTMI_CLK_ARES 199
#define GCC_USB1_PHY_CFG_AHB_CLK_ARES 200
#define GCC_USB1_SLEEP_CLK_ARES 201
#define GCC_USB3PHY_0_PHY_BCR 202
#define GCC_USB_BCR 203
#define GCC_UNIPHY1_XLGPCS_ARES 204
#define GCC_UNIPHY2_XLGPCS_ARES 205
#endif

6
include/linux/interconnect.h
View File

@@ -47,6 +47,7 @@ struct icc_path *of_icc_get(struct device *dev, const char *name);
struct icc_path *devm_of_icc_get(struct device *dev, const char *name);
int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths);
struct icc_path *of_icc_get_by_index(struct device *dev, int idx);
struct icc_path *devm_of_icc_get_by_index(struct device *dev, int idx);
void icc_put(struct icc_path *path);
int icc_enable(struct icc_path *path);
int icc_disable(struct icc_path *path);
@@ -79,6 +80,11 @@ static inline struct icc_path *of_icc_get_by_index(struct device *dev, int idx)
return NULL;
}
static inline struct icc_path *devm_of_icc_get_by_index(struct device *dev, int idx)
{
return NULL;
}
static inline void icc_put(struct icc_path *path)
{
}