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drm/amd/display: Update panel register

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[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.

[How]
Implement same register space to future
resource files.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chris Park
2020-10-19 14:32:14 -04:00
committed by Alex Deucher
parent 7dd4f4df99
commit 91bda9e9d2
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
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@@ -967,7 +967,7 @@ static const struct encoder_feature_support link_enc_feature = {
[id] = {\
LE_DCN3_REG_LIST(id), \
UNIPHY_DCN2_REG_LIST(phyid), \
DPCS_DCN2_REG_LIST(id), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}
static const struct dcn10_link_enc_registers link_enc_regs[] = {