mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-05 07:30:06 -04:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: exynos: add prefetch properties for L2C-310 cache

Browse Source 
Add the devicetree properties to enable instruction and data prefetch
on exynos4210 and exynos4412 which use the L2C-310 cache.  No other
Exynos chip appears to be using this L2 cache hardware.

This follows the default bits being set in the l2c_aux_val register
for the Exynos platform, which can now be cleared as a result.

Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Guillaume Tucker
2020-08-10 13:22:07 +01:00
committed by Krzysztof Kozlowski
parent a084c9d204
commit 91b440ed25
2 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/exynos4210.dtsi
View File

@@ -102,6 +102,8 @@ l2c: cache-controller@10502000 {
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
prefetch-data = <1>;
prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>;
};

2
arch/arm/boot/dts/exynos4412.dtsi
View File

@@ -218,6 +218,8 @@ l2c: cache-controller@10502000 {
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
prefetch-data = <1>;
prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <3 2 1>;
arm,double-linefill = <1>;