gpu: nova-core: fb: Move PDISP register definition

Move PDISP register definition into fb module and update register
visibility.

Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
Link: https://patch.msgid.link/20260617-nova-core-regs-split-v1-1-4c7dc4450ea7@nanonej.com
[acourbot: fix rustfmt issue.]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
This commit is contained in:
Antonin Malzieu Ridolfi
2026-06-17 01:48:12 +02:00
committed by Alexandre Courbot
parent 917e43d72e
commit 9102e655ea
3 changed files with 27 additions and 24 deletions

View File

@@ -23,11 +23,11 @@
firmware::gsp::GspFirmware,
gpu::Chipset,
gsp,
num::FromSafeCast,
regs, //
num::FromSafeCast, //
};
mod hal;
mod regs;
/// Type holding the sysmem flush memory page, a page of memory to be written into the
/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory coherency.

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@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
use kernel::io::register;
// PDISP
register! {
pub(super) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 {
/// VGA workspace base address divided by 0x10000.
31:8 addr;
/// Set if the `addr` field is valid.
3:3 status_valid => bool;
}
}
impl NV_PDISP_VGA_WORKSPACE_BASE {
/// Returns the base address of the VGA workspace, or `None` if none exists.
pub(super) fn vga_workspace_addr(self) -> Option<u64> {
if self.status_valid() {
Some(u64::from(self.addr()) << 16)
} else {
None
}
}
}

View File

@@ -302,28 +302,6 @@ pub(crate) fn usable_fb_size(self) -> u64 {
}
}
// PDISP
register! {
pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 {
/// VGA workspace base address divided by 0x10000.
31:8 addr;
/// Set if the `addr` field is valid.
3:3 status_valid => bool;
}
}
impl NV_PDISP_VGA_WORKSPACE_BASE {
/// Returns the base address of the VGA workspace, or `None` if none exists.
pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
if self.status_valid() {
Some(u64::from(self.addr()) << 16)
} else {
None
}
}
}
// FUSE
pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16;