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PCI: mediatek-gen3: Move reset delay in mtk_pcie_en7581_power_up()

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Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
causing occasional PCIe link down issues. In order to overcome the
problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and
REG_RESET_CONTROL (0x834) registers available in the clock module
running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up().

In order to make the code more readable, move the wait for the time
needed to complete the PCIe reset from en7581_pci_enable() to
mtk_pcie_en7581_power_up().

Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value
(100ms) since it has no impact on the driver behavior.

Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-4-21ac939a3b9b@kernel.org
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lorenzo Bianconi
2025-01-08 10:50:43 +01:00
committed by Krzysztof Wilczyński
parent 0c9d2d2ef0
commit 90d4e466c9
2 changed files with 7 additions and 1 deletions
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1
drivers/clk/clk-en7523.c
View File

@@ -477,7 +477,6 @@ static int en7581_pci_enable(struct clk_hw *hw)
REG_PCI_CONTROL_PERSTOUT;
val = readl(np_base + REG_PCI_CONTROL);
writel(val | mask, np_base + REG_PCI_CONTROL);
msleep(250);
return 0;
}

7
drivers/pci/controller/pcie-mediatek-gen3.c
View File

@@ -974,6 +974,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
goto err_clk_prepare_enable;
}
/*
* Airoha EN7581 performs PCIe reset via clk callbacks since it has a
* hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to
* complete the PCIe reset.
*/
msleep(PCIE_T_PVPERL_MS);
return 0;
err_clk_prepare_enable: