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riscv: dts: sophgo: reduce SG2042 MSI count to 16

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The SG2042 MSI controller has one 32-bit doorbell register, and each bit
corresponds to an interrupt. At a glance, it seems that the MSI
controller can support 32 interrupts; however the PCI MSI capability
only supports 16-bit messages, which makes the high 16 interrupts
unusable in such way.

Reduce the MSI count to 16 to prevent producing MSI message values that
cannot fit 16-bit integers.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Icenowy Zheng
2026-04-08 00:01:43 +08:00
committed by Inochi Amaoto
parent a7e6589076
commit 903a9364e4
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 {
reg-names = "clr", "doorbell";
msi-controller;
#msi-cells = <0>;
msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>;
msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
};
rpgate: clock-controller@7030010368 {