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serial: sh-sci: Add support for RZ/G3L RSCI
Add support for RZ/G3L RSCI. The RSCI IP found on the RZ/G3L SoC is similar to RZ/G3E, but it has 3 clocks (2 module clocks + 1 external clock) instead of 6 clocks (5 module clocks + 1 external clock) on the RZ/G3E. Both RZ/G3L and RZ/G3E have a 32-bit FIFO, but RZ/G3L has a single TCLK with internal dividers, whereas the RZ/G3E has explicit clocks for TCLK and its dividers. Add a new port type RSCI_PORT_SCIF32_SINGLE_TCLK to handle this clock difference. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260312082708.98835-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
6672462c97
commit
8f18d3cbd9
@@ -695,6 +695,13 @@ struct sci_of_data of_rsci_rzg3e_data = {
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.params = &rsci_rzg3e_port_params,
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};
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struct sci_of_data of_rsci_rzg3l_data = {
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.type = RSCI_PORT_SCIF32_SINGLE_TCLK,
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.ops = &rsci_port_ops,
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.uart_ops = &rsci_uart_ops,
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.params = &rsci_rzg3e_port_params,
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};
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struct sci_of_data of_rsci_rzt2h_data = {
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.type = RSCI_PORT_SCIF16,
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.ops = &rsci_port_ops,
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@@ -703,6 +710,11 @@ struct sci_of_data of_rsci_rzt2h_data = {
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};
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#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
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static int __init rsci_rzg3l_early_console_setup(struct earlycon_device *device,
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const char *opt)
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{
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return scix_early_console_setup(device, &of_rsci_rzg3l_data);
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}
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static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device,
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const char *opt)
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@@ -716,6 +728,7 @@ static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device,
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return scix_early_console_setup(device, &of_rsci_rzt2h_data);
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}
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OF_EARLYCON_DECLARE(rsci, "renesas,r9a08g046-rsci", rsci_rzg3l_early_console_setup);
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OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup);
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OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup);
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@@ -6,6 +6,7 @@
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#include "sh-sci-common.h"
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extern struct sci_of_data of_rsci_rzg3e_data;
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extern struct sci_of_data of_rsci_rzg3l_data;
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extern struct sci_of_data of_rsci_rzt2h_data;
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#endif /* __RSCI_H__ */
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@@ -9,6 +9,7 @@
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enum SCI_PORT_TYPE {
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RSCI_PORT_SCIF16 = BIT(7) | 0,
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RSCI_PORT_SCIF32 = BIT(7) | 1,
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RSCI_PORT_SCIF32_SINGLE_TCLK = BIT(7) | 2,
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};
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enum SCI_CLKS {
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@@ -1184,7 +1184,8 @@ static int sci_handle_errors(struct uart_port *port)
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static bool sci_is_rsci_type(u8 type)
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{
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return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32);
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return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32 ||
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type == RSCI_PORT_SCIF32_SINGLE_TCLK);
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}
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static int sci_handle_fifo_overrun(struct uart_port *port)
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@@ -3181,7 +3182,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
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if (sci_port->type == PORT_HSCIF) {
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clk_names[SCI_SCK] = "hsck";
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} else if (sci_port->type == RSCI_PORT_SCIF16) {
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} else if (sci_port->type == RSCI_PORT_SCIF16 ||
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sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) {
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clk_names[SCI_FCK] = "operation";
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clk_names[SCI_BRG_INT] = "bus";
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} else if (sci_port->type == RSCI_PORT_SCIF32) {
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@@ -3196,7 +3198,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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if (!clk && sci_port->type == RSCI_PORT_SCIF16 &&
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if (!clk && (sci_port->type == RSCI_PORT_SCIF16 ||
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sci_port->type == RSCI_PORT_SCIF32_SINGLE_TCLK) &&
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(i == SCI_FCK || i == SCI_BRG_INT))
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return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
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@@ -3330,6 +3333,7 @@ static int sci_init_single(struct platform_device *dev,
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break;
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case PORT_SCIFA:
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case RSCI_PORT_SCIF32:
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case RSCI_PORT_SCIF32_SINGLE_TCLK:
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sci_port->rx_trigger = 32;
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break;
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case PORT_SCIF:
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@@ -3663,6 +3667,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
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.data = &of_sci_scif_rzv2h,
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},
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#ifdef CONFIG_SERIAL_RSCI
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{
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.compatible = "renesas,r9a08g046-rsci",
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.data = &of_rsci_rzg3l_data,
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},
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{
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.compatible = "renesas,r9a09g047-rsci",
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.data = &of_rsci_rzg3e_data,
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