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arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support

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The Liontron H-A133L board features an Ethernet controller with a
JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO.

Note that the reset pin must be handled as a bus-wide reset GPIO in
order to let the MDIO core properly reset it before trying to read
its identification registers. There's no other device on the MDIO bus.

The datasheet of the PHY mentions that the reset signal must be held
for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to
be on the safe side without wasting too much time during boot.

Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250707165155.581579-5-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Paul Kocialkowski
2025-07-07 18:51:55 +02:00
committed by Chen-Yu Tsai
parent 4e3be5629f
commit 8f128f357d
1 changed files with 19 additions and 0 deletions
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19
arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
View File

@@ -65,6 +65,25 @@ &ehci1 {
status = "okay";
};
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&rmii0_pins>;
phy-handle = <&rmii_phy>;
phy-mode = "rmii";
status = "okay";
};
&mdio0 {
reset-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */
reset-delay-us = <2000>;
reset-post-delay-us = <2000>;
rmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */