wifi: rtw89: pci: disable PCI PHY error flag 8

As the PHY error flag 8 works improperly, disable it to prevent false
alarm causing SER.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260515014433.16168-7-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
2026-05-15 09:44:26 +08:00
parent e0bb1246e3
commit 8ee752289e
2 changed files with 6 additions and 1 deletions

View File

@@ -58,7 +58,7 @@
#define B_AX_DIV GENMASK(15, 14)
#define RAC_SET_PPR_V1 0x31
#define RAC_ANA40 0x40
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(0))
#define PHY_ERR_IMR_DIS (BIT(9) | BIT(8) | BIT(0))
#define RAC_ANA41 0x41
#define PHY_ERR_FLAG_EN BIT(6)
@@ -963,6 +963,8 @@
#define R_BE_PCIE_HRPWM 0x30C0
#define R_BE_PCIE_CRPWM 0x30C4
#define R_BE_PCIE_HCI2FW_ISR 0x30CC
#define R_BE_L1_2_CTRL_HCILDO 0x3110
#define B_BE_PM_CLKREQ_EXT_RB BIT(11)
#define B_BE_PCIE_DIS_RTK_PRST_N_L1_2 BIT(10)

View File

@@ -347,6 +347,7 @@ static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
}
static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
@@ -843,6 +844,8 @@ static int __maybe_unused rtw89_pci_resume_be(struct device *dev)
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
}
rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
}
rtw89_pci_basic_cfg(rtwdev, true);