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arm64: dts: r8a7795: Add CA53 L2 cache-controller node

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Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
2015-09-30 15:22:15 +02:00
committed by Simon Horman
parent a528b4bf1a
commit 8e1c3aa30c
1 changed files with 6 additions and 0 deletions
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arch/arm64/boot/dts/renesas/r8a7795.dtsi
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@@ -72,6 +72,12 @@ L2_CA57: cache-controller@0 {
cache-level = <2>;
};
L2_CA53: cache-controller@1 {
compatible = "cache";
cache-unified;
cache-level = <2>;
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;