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drm/i915: Move M/N setup to a more logical place on ddi platforms

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Let's do the cpu transcoder M/N setup next to where we program
most other cpu transcoder timings/etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2022-01-28 12:37:48 +02:00
parent a68819cc55
commit 8de5df3b07
3 changed files with 11 additions and 17 deletions
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10
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@@ -2498,8 +2498,6 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2509,14 +2507,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* MST will call a setting of MSA after an allocating of Virtual Channel
* from MST encoder pre_enable callback.
*/
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&crtc_state->dp_m2_n2);
}
}
static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,

14
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -2003,16 +2003,22 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (crtc_state->has_pch_encoder) {
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->fdi_m_n);
} else if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
&crtc_state->dp_m2_n2);
}
intel_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
crtc_state->pixel_multiplier - 1);
if (crtc_state->has_pch_encoder)
intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
&crtc_state->fdi_m_n);
hsw_set_frame_start_delay(crtc_state);
hsw_set_transconf(crtc_state);

4
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@@ -473,7 +473,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
struct intel_digital_port *dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
int ret;
@@ -523,9 +522,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_pipe_clock(encoder, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
intel_cpu_transcoder_set_m1_n1(crtc, pipe_config->cpu_transcoder,
&pipe_config->dp_m_n);
}
static void intel_mst_enable_dp(struct intel_atomic_state *state,