mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-04-04 15:55:59 -04:00
Merge ACPICA material for 6.20 to satisfy dependencies
This commit is contained in:
@@ -587,6 +587,9 @@ const union acpi_predefined_info acpi_gbl_predefined_methods[] = {
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METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}}, /* Variable-length (Pkgs) each (var Ints) */
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PACKAGE_INFO(ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5, 0, 0, 0),
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{{"_VDM", METHOD_0ARGS,
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METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
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{{"_HRV", METHOD_0ARGS,
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METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
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@@ -163,7 +163,9 @@ acpi_ev_address_space_dispatch(union acpi_operand_object *region_obj,
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return_ACPI_STATUS(AE_NOT_EXIST);
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}
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if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
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if (field_obj
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&& region_obj->region.space_id ==
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ACPI_ADR_SPACE_PLATFORM_COMM) {
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struct acpi_pcc_info *ctx =
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handler_desc->address_space.context;
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@@ -10,6 +10,7 @@
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#include <acpi/acpi.h>
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#include "accommon.h"
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#include "acinterp.h"
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#include <acpi/acoutput.h>
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#include "acparser.h"
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#include "amlcode.h"
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@@ -51,8 +52,7 @@ ACPI_MODULE_NAME("exoparg3")
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acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
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{
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union acpi_operand_object **operand = &walk_state->operands[0];
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struct acpi_signal_fatal_info *fatal;
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acpi_status status = AE_OK;
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struct acpi_signal_fatal_info fatal;
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ACPI_FUNCTION_TRACE_STR(ex_opcode_3A_0T_0R,
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acpi_ps_get_opcode_name(walk_state->opcode));
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@@ -60,28 +60,30 @@ acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
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switch (walk_state->opcode) {
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case AML_FATAL_OP: /* Fatal (fatal_type fatal_code fatal_arg) */
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"FatalOp: Type %X Code %X Arg %X "
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"<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n",
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(u32)operand[0]->integer.value,
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(u32)operand[1]->integer.value,
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(u32)operand[2]->integer.value));
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fatal.type = (u32)operand[0]->integer.value;
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fatal.code = (u32)operand[1]->integer.value;
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fatal.argument = (u32)operand[2]->integer.value;
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fatal = ACPI_ALLOCATE(sizeof(struct acpi_signal_fatal_info));
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if (fatal) {
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fatal->type = (u32) operand[0]->integer.value;
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fatal->code = (u32) operand[1]->integer.value;
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fatal->argument = (u32) operand[2]->integer.value;
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}
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ACPI_BIOS_ERROR((AE_INFO,
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"Fatal ACPI BIOS error (Type 0x%X Code 0x%X Arg 0x%X)\n",
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fatal.type, fatal.code, fatal.argument));
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/* Always signal the OS! */
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status = acpi_os_signal(ACPI_SIGNAL_FATAL, fatal);
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acpi_os_signal(ACPI_SIGNAL_FATAL, &fatal);
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/* Might return while OS is shutting down, just continue */
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ACPI_FREE(fatal);
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goto cleanup;
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#ifndef ACPI_CONTINUE_ON_FATAL
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/*
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* Might return while OS is shutting down, so abort the AML execution
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* by returning an error.
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*/
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return_ACPI_STATUS(AE_ERROR);
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#else
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/*
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* The alstests require that the Fatal() opcode does not return an error.
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*/
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return_ACPI_STATUS(AE_OK);
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#endif
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case AML_EXTERNAL_OP:
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/*
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@@ -93,21 +95,16 @@ acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
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* wrong if an external opcode ever gets here.
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*/
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ACPI_ERROR((AE_INFO, "Executed External Op"));
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status = AE_OK;
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goto cleanup;
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return_ACPI_STATUS(AE_OK);
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default:
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ACPI_ERROR((AE_INFO, "Unknown AML opcode 0x%X",
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walk_state->opcode));
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status = AE_AML_BAD_OPCODE;
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goto cleanup;
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return_ACPI_STATUS(AE_AML_BAD_OPCODE);
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}
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cleanup:
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return_ACPI_STATUS(status);
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}
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/*******************************************************************************
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@@ -601,7 +601,7 @@ acpi_status acpi_install_method(u8 *buffer)
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error_exit:
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ACPI_FREE(aml_buffer);
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ACPI_FREE(method_obj);
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acpi_ut_delete_object_desc(method_obj);
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return (status);
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}
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ACPI_EXPORT_SYMBOL(acpi_install_method)
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@@ -148,7 +148,7 @@ union acpi_operand_object *acpi_ut_create_package_object(u32 count)
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package_elements = ACPI_ALLOCATE_ZEROED(((acpi_size)count +
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1) * sizeof(void *));
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if (!package_elements) {
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ACPI_FREE(package_desc);
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acpi_ut_delete_object_desc(package_desc);
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return_PTR(NULL);
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}
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@@ -92,7 +92,11 @@ static struct acpi_interface_info acpi_default_supported_interfaces[] = {
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{"Processor Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
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{"3.0 Thermal Model", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
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{"3.0 _SCP Extensions", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
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{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
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{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
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/* See https://learn.microsoft.com/en-us/windows-hardware/drivers/display/automatic-display-switch */
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{"DisplayMux", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
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};
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/*******************************************************************************
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@@ -12,7 +12,7 @@
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/* Current ACPICA subsystem version in YYYYMMDD format */
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#define ACPI_CA_VERSION 0x20250807
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#define ACPI_CA_VERSION 0x20251212
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#include <acpi/acconfig.h>
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#include <acpi/actypes.h>
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@@ -37,6 +37,7 @@
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#define ACPI_SIG_DBGP "DBGP" /* Debug Port table */
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#define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */
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#define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */
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#define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */
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#define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */
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#define ACPI_SIG_EINJ "EINJ" /* Error Injection table */
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#define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */
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@@ -999,6 +1000,262 @@ struct acpi_drtm_dps_id {
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u8 dps_id[16];
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};
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/*******************************************************************************
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*
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* DTPR - DMA TXT Protection Ranges Table
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* Version 1
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*
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* Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
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* Ranges",
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* Revision 0.73, August 2021
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*
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******************************************************************************/
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struct acpi_table_dtpr {
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struct acpi_table_header header;
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u32 flags; /* 36 */
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u32 ins_cnt;
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};
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struct acpi_tpr_array {
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u64 base;
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};
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struct acpi_tpr_instance {
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u32 flags;
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u32 tpr_cnt;
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};
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struct acpi_tpr_aux_sr {
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u32 srl_cnt;
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};
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/*
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* TPRn_BASE (ACPI_TPRN_BASE_REG)
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*
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* Specifies the start address of TPRn region. TPR region address and size must
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* be with 1MB resolution. These bits are compared with the result of the
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* TPRn_LIMIT[63:20], which is applied to the incoming address, to
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* determine if an access fall within the TPRn defined region.
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*
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* Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to
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* determine if an access fall within the TPRn defined region. Width is
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* determined by a bus width which can be obtained via CPUID
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* function 0x80000008.
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*/
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typedef u64 ACPI_TPRN_BASE_REG;
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/* TPRn_BASE Register Bit Masks */
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/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
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#define ACPI_TPRN_BASE_RW_SHIFT 3
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#define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT)
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/*
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* Bit 4 - Enable: 0 – TPRn address range enabled;
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* 1 – TPRn address range disabled.
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*/
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#define ACPI_TPRN_BASE_ENABLE_SHIFT 4
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#define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT)
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/* Bits 63:20 - tpr_base_rw */
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#define ACPI_TPRN_BASE_ADDR_SHIFT 20
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#define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \
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ACPI_TPRN_BASE_ADDR_SHIFT)
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/* TPRn_BASE Register Bit Handlers*/
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/*
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* GET_TPRN_BASE_RW:
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*
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* Read RW bit from TPRn Base register - bit 3.
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*
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* Input:
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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*
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* Output:
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*
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* Returns RW bit value (u64).
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*/
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#define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \
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ACPI_TPRN_BASE_RW_SHIFT)
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/*
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* GET_TPRN_BASE_ENABLE:
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*
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* Read Enable bit from TPRn Base register - bit 4.
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*
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* Input:
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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*
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* Output:
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*
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* Returns Enable bit value (u64).
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*/
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#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \
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>> ACPI_TPRN_BASE_ENABLE_SHIFT)
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/*
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* GET_TPRN_BASE_ADDR:
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*
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* Read TPRn Base Register address from bits 63:20.
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*
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* Input:
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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*
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* Output:
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*
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* Returns TPRn Base Register address (u64).
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*/
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#define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \
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>> ACPI_TPRN_BASE_ADDR_SHIFT)
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/*
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* SET_TPRN_BASE_RW:
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*
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* Set RW bit in TPRn Base register - bit 3.
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*
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* Input:
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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* - val (represents RW value to be set (u64))
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*/
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#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
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ACPI_TPRN_BASE_RW_SHIFT, \
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ACPI_TPRN_BASE_RW_MASK, val);
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/*
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* SET_TPRN_BASE_ENABLE:
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*
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* Set Enable bit in TPRn Base register - bit 4.
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*
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* Input:
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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* - val (represents Enable value to be set (u64))
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*/
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#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
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ACPI_TPRN_BASE_ENABLE_SHIFT, \
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ACPI_TPRN_BASE_ENABLE_MASK, val);
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/*
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* SET_TPRN_BASE_ADDR:
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*
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* Set TPRn Base Register address - bits 63:20
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*
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* Input
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* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
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* - val (represents address value to be set (u64))
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*/
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#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
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ACPI_TPRN_BASE_ADDR_SHIFT, \
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ACPI_TPRN_BASE_ADDR_MASK, val);
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/*
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* TPRn_LIMIT
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*
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* This register defines an isolated region of memory that can be enabled
|
||||
* to prohibit certain system agents from accessing memory. When an agent
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* sends a request upstream, whether snooped or not, a TPR prevents that
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* transaction from changing the state of memory.
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*
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* Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width.
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*/
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typedef u64 ACPI_TPRN_LIMIT_REG;
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/* TPRn_LIMIT Register Bit Masks */
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/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
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#define ACPI_TPRN_LIMIT_RW_SHIFT 3
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#define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT)
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/* Bits 63:20 - tpr_limit_rw */
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#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20
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#define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \
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ACPI_TPRN_LIMIT_ADDR_SHIFT)
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/* TPRn_LIMIT Register Bit Handlers*/
|
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/*
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* GET_TPRN_LIMIT_RW:
|
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*
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* Read RW bit from TPRn Limit register - bit 3.
|
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*
|
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* Input:
|
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* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
|
||||
*
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* Output:
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*
|
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* Returns RW bit value (u64).
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||||
*/
|
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#define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \
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>> ACPI_TPRN_LIMIT_RW_SHIFT)
|
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|
||||
/*
|
||||
* GET_TPRN_LIMIT_ADDR:
|
||||
*
|
||||
* Read TPRn Limit Register address from bits 63:20.
|
||||
*
|
||||
* Input:
|
||||
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
|
||||
*
|
||||
* Output:
|
||||
*
|
||||
* Returns TPRn Limit Register address (u64).
|
||||
*/
|
||||
#define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \
|
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>> ACPI_TPRN_LIMIT_ADDR_SHIFT)
|
||||
|
||||
/*
|
||||
* SET_TPRN_LIMIT_RW:
|
||||
*
|
||||
* Set RW bit in TPRn Limit register - bit 3.
|
||||
*
|
||||
* Input:
|
||||
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
|
||||
* - val (represents RW value to be set (u64))
|
||||
*/
|
||||
#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
|
||||
ACPI_TPRN_LIMIT_RW_SHIFT, \
|
||||
ACPI_TPRN_LIMIT_RW_MASK, val);
|
||||
|
||||
/*
|
||||
* SET_TPRN_LIMIT_ADDR:
|
||||
*
|
||||
* Set TPRn Limit Register address - bits 63:20.
|
||||
*
|
||||
* Input:
|
||||
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
|
||||
* - val (represents address value to be set (u64))
|
||||
*/
|
||||
#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
|
||||
ACPI_TPRN_LIMIT_ADDR_SHIFT, \
|
||||
ACPI_TPRN_LIMIT_ADDR_MASK, val);
|
||||
|
||||
/*
|
||||
* SERIALIZE_REQUEST
|
||||
*
|
||||
* This register is used to request serialization of non-coherent DMA
|
||||
* transactions. OS shall issue it before changing of TPR settings
|
||||
* (base / size).
|
||||
*/
|
||||
|
||||
struct acpi_tpr_serialize_request {
|
||||
u64 sr_register;
|
||||
/*
|
||||
* BIT 1 - Status of serialization request (RO)
|
||||
* 0 == register idle, 1 == serialization in progress
|
||||
* BIT 2 - Control field to initiate serialization (RW)
|
||||
* 0 == normal, 1 == initialize serialization
|
||||
* (self-clear to allow multiple serialization requests)
|
||||
*/
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* ECDT - Embedded Controller Boot Resources Table
|
||||
|
||||
@@ -31,7 +31,9 @@
|
||||
#define ACPI_SIG_CDAT "CDAT" /* Coherent Device Attribute Table */
|
||||
#define ACPI_SIG_ERDT "ERDT" /* Enhanced Resource Director Technology */
|
||||
#define ACPI_SIG_IORT "IORT" /* IO Remapping Table */
|
||||
#define ACPI_SIG_IOVT "IOVT" /* I/O Virtualization Table */
|
||||
#define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */
|
||||
#define ACPI_SIG_KEYP "KEYP" /* Key Programming Interface for IDE */
|
||||
#define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */
|
||||
#define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
|
||||
#define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */
|
||||
@@ -680,6 +682,7 @@ enum acpi_iort_node_type {
|
||||
ACPI_IORT_NODE_SMMU_V3 = 0x04,
|
||||
ACPI_IORT_NODE_PMCG = 0x05,
|
||||
ACPI_IORT_NODE_RMR = 0x06,
|
||||
ACPI_IORT_NODE_IWB = 0x07,
|
||||
};
|
||||
|
||||
struct acpi_iort_id_mapping {
|
||||
@@ -858,6 +861,79 @@ struct acpi_iort_rmr_desc {
|
||||
u32 reserved;
|
||||
};
|
||||
|
||||
struct acpi_iort_iwb {
|
||||
u64 base_address;
|
||||
u16 iwb_index; /* Unique IWB identifier matching with the IWB GSI namespace. */
|
||||
char device_name[]; /* Path of the IWB namespace object */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* IOVT - I/O Virtualization Table
|
||||
*
|
||||
* Conforms to "LoongArch I/O Virtualization Table",
|
||||
* Version 0.1, October 2024
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
struct acpi_table_iovt {
|
||||
struct acpi_table_header header; /* Common ACPI table header */
|
||||
u16 iommu_count;
|
||||
u16 iommu_offset;
|
||||
u8 reserved[8];
|
||||
};
|
||||
|
||||
/* IOVT subtable header */
|
||||
|
||||
struct acpi_iovt_header {
|
||||
u16 type;
|
||||
u16 length;
|
||||
};
|
||||
|
||||
/* Values for Type field above */
|
||||
|
||||
enum acpi_iovt_iommu_type {
|
||||
ACPI_IOVT_IOMMU_V1 = 0x00,
|
||||
ACPI_IOVT_IOMMU_RESERVED = 0x01 /* 1 and greater are reserved */
|
||||
};
|
||||
|
||||
/* IOVT subtables */
|
||||
|
||||
struct acpi_iovt_iommu {
|
||||
struct acpi_iovt_header header;
|
||||
u32 flags;
|
||||
u16 segment;
|
||||
u16 phy_width; /* Physical Address Width */
|
||||
u16 virt_width; /* Virtual Address Width */
|
||||
u16 max_page_level;
|
||||
u64 page_size;
|
||||
u32 device_id;
|
||||
u64 base_address;
|
||||
u32 address_space_size;
|
||||
u8 interrupt_type;
|
||||
u8 reserved[3];
|
||||
u32 gsi_number;
|
||||
u32 proximity_domain;
|
||||
u32 max_device_num;
|
||||
u32 device_entry_num;
|
||||
u32 device_entry_offset;
|
||||
};
|
||||
|
||||
struct acpi_iovt_device_entry {
|
||||
u8 type;
|
||||
u8 length;
|
||||
u8 flags;
|
||||
u8 reserved[3];
|
||||
u16 device_id;
|
||||
};
|
||||
|
||||
enum acpi_iovt_device_entry_type {
|
||||
ACPI_IOVT_DEVICE_ENTRY_SINGLE = 0x00,
|
||||
ACPI_IOVT_DEVICE_ENTRY_START = 0x01,
|
||||
ACPI_IOVT_DEVICE_ENTRY_END = 0x02,
|
||||
ACPI_IOVT_DEVICE_ENTRY_RESERVED = 0x03 /* 3 and greater are reserved */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* IVRS - I/O Virtualization Reporting Structure
|
||||
@@ -1065,6 +1141,64 @@ struct acpi_ivrs_memory {
|
||||
u64 memory_length;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* KEYP - Key Programming Interface for Root Complex Integrity and Data
|
||||
* Encryption (IDE)
|
||||
* Version 1
|
||||
*
|
||||
* Conforms to "Key Programming Interface for Root Complex Integrity and Data
|
||||
* Encryption (IDE)" document. See under ACPI-Related Documents.
|
||||
*
|
||||
******************************************************************************/
|
||||
struct acpi_table_keyp {
|
||||
struct acpi_table_header header; /* Common ACPI table header */
|
||||
u32 reserved;
|
||||
};
|
||||
|
||||
/* KEYP common subtable header */
|
||||
|
||||
struct acpi_keyp_common_header {
|
||||
u8 type;
|
||||
u8 reserved;
|
||||
u16 length;
|
||||
};
|
||||
|
||||
/* Values for Type field above */
|
||||
|
||||
enum acpi_keyp_type {
|
||||
ACPI_KEYP_TYPE_CONFIG_UNIT = 0,
|
||||
};
|
||||
|
||||
/* Root Port Information Structure */
|
||||
|
||||
struct acpi_keyp_rp_info {
|
||||
u16 segment;
|
||||
u8 bus;
|
||||
u8 devfn;
|
||||
};
|
||||
|
||||
/* Key Configuration Unit Structure */
|
||||
|
||||
struct acpi_keyp_config_unit {
|
||||
struct acpi_keyp_common_header header;
|
||||
u8 protocol_type;
|
||||
u8 version;
|
||||
u8 root_port_count;
|
||||
u8 flags;
|
||||
u64 register_base_address;
|
||||
struct acpi_keyp_rp_info rp_info[];
|
||||
};
|
||||
|
||||
enum acpi_keyp_protocol_type {
|
||||
ACPI_KEYP_PROTO_TYPE_INVALID = 0,
|
||||
ACPI_KEYP_PROTO_TYPE_PCIE,
|
||||
ACPI_KEYP_PROTO_TYPE_CXL,
|
||||
ACPI_KEYP_PROTO_TYPE_RESERVED
|
||||
};
|
||||
|
||||
#define ACPI_KEYP_F_TVM_USABLE (1)
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* LPIT - Low Power Idle Table
|
||||
@@ -1167,7 +1301,10 @@ enum acpi_madt_type {
|
||||
ACPI_MADT_TYPE_IMSIC = 25,
|
||||
ACPI_MADT_TYPE_APLIC = 26,
|
||||
ACPI_MADT_TYPE_PLIC = 27,
|
||||
ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */
|
||||
ACPI_MADT_TYPE_GICV5_IRS = 28,
|
||||
ACPI_MADT_TYPE_GICV5_ITS = 29,
|
||||
ACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,
|
||||
ACPI_MADT_TYPE_RESERVED = 31, /* 31 to 0x7F are reserved */
|
||||
ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */
|
||||
};
|
||||
|
||||
@@ -1289,7 +1426,7 @@ struct acpi_madt_local_x2apic_nmi {
|
||||
u8 reserved[3]; /* reserved - must be zero */
|
||||
};
|
||||
|
||||
/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */
|
||||
/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 + ACPI 6.7 changes) */
|
||||
|
||||
struct acpi_madt_generic_interrupt {
|
||||
struct acpi_subtable_header header;
|
||||
@@ -1310,6 +1447,8 @@ struct acpi_madt_generic_interrupt {
|
||||
u8 reserved2[1];
|
||||
u16 spe_interrupt; /* ACPI 6.3 */
|
||||
u16 trbe_interrupt; /* ACPI 6.5 */
|
||||
u16 iaffid; /* ACPI 6.7 */
|
||||
u32 irs_id;
|
||||
};
|
||||
|
||||
/* Masks for Flags field above */
|
||||
@@ -1332,7 +1471,7 @@ struct acpi_madt_generic_distributor {
|
||||
u8 reserved2[3]; /* reserved - must be zero */
|
||||
};
|
||||
|
||||
/* Values for Version field above */
|
||||
/* Values for Version field above and Version field in acpi_madt_gicv5_irs */
|
||||
|
||||
enum acpi_madt_gic_version {
|
||||
ACPI_MADT_GIC_VERSION_NONE = 0,
|
||||
@@ -1340,7 +1479,8 @@ enum acpi_madt_gic_version {
|
||||
ACPI_MADT_GIC_VERSION_V2 = 2,
|
||||
ACPI_MADT_GIC_VERSION_V3 = 3,
|
||||
ACPI_MADT_GIC_VERSION_V4 = 4,
|
||||
ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */
|
||||
ACPI_MADT_GIC_VERSION_V5 = 5,
|
||||
ACPI_MADT_GIC_VERSION_RESERVED = 6 /* 6 and greater are reserved */
|
||||
};
|
||||
|
||||
/* 13: Generic MSI Frame (ACPI 5.1) */
|
||||
@@ -1611,6 +1751,41 @@ struct acpi_madt_plic {
|
||||
u32 gsi_base;
|
||||
};
|
||||
|
||||
/* 28: Arm GICv5 IRS (ACPI 6.7) */
|
||||
struct acpi_madt_gicv5_irs {
|
||||
struct acpi_subtable_header header;
|
||||
u8 version;
|
||||
u8 reserved;
|
||||
u32 irs_id;
|
||||
u32 flags;
|
||||
u32 reserved2;
|
||||
u64 config_base_address;
|
||||
u64 setlpi_base_address;
|
||||
};
|
||||
|
||||
#define ACPI_MADT_IRS_NON_COHERENT (1)
|
||||
|
||||
/* 29: Arm GICv5 ITS Config Frame (ACPI 6.7) */
|
||||
struct acpi_madt_gicv5_translator {
|
||||
struct acpi_subtable_header header;
|
||||
u8 flags;
|
||||
u8 reserved; /* reserved - must be zero */
|
||||
u32 translator_id;
|
||||
u64 base_address;
|
||||
};
|
||||
|
||||
#define ACPI_MADT_GICV5_ITS_NON_COHERENT (1)
|
||||
|
||||
/* 30: Arm GICv5 ITS Translate Frame (ACPI 6.7) */
|
||||
struct acpi_madt_gicv5_translate_frame {
|
||||
struct acpi_subtable_header header;
|
||||
u16 reserved; /* reserved - must be zero */
|
||||
u32 linked_translator_id;
|
||||
u32 translate_frame_id;
|
||||
u32 reserved2;
|
||||
u64 base_address;
|
||||
};
|
||||
|
||||
/* 80: OEM data */
|
||||
|
||||
struct acpi_madt_oem_data {
|
||||
@@ -2826,6 +3001,15 @@ struct acpi_pptt_cache {
|
||||
/* 1: Cache Type Structure for PPTT version 3 */
|
||||
|
||||
struct acpi_pptt_cache_v1 {
|
||||
struct acpi_subtable_header header;
|
||||
u16 reserved;
|
||||
u32 flags;
|
||||
u32 next_level_of_cache;
|
||||
u32 size;
|
||||
u32 number_of_sets;
|
||||
u8 associativity;
|
||||
u8 attributes;
|
||||
u16 line_size;
|
||||
u32 cache_id;
|
||||
};
|
||||
|
||||
@@ -3065,6 +3249,8 @@ struct acpi_ras2_patrol_scrub_param {
|
||||
u32 flags;
|
||||
u32 scrub_params_out;
|
||||
u32 scrub_params_in;
|
||||
u32 ext_scrub_params;
|
||||
u8 scrub_rate_desc[256];
|
||||
};
|
||||
|
||||
/* Masks for Flags field above */
|
||||
|
||||
@@ -238,6 +238,7 @@ struct acpi_srat_mem_affinity {
|
||||
#define ACPI_SRAT_MEM_ENABLED (1) /* 00: Use affinity structure */
|
||||
#define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1) /* 01: Memory region is hot pluggable */
|
||||
#define ACPI_SRAT_MEM_NON_VOLATILE (1<<2) /* 02: Memory region is non-volatile */
|
||||
#define ACPI_SRAT_MEM_SPEC_PURPOSE (1<<3) /* 03: Memory is intended for specific-purpose usage */
|
||||
|
||||
/* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */
|
||||
|
||||
|
||||
@@ -37,6 +37,11 @@
|
||||
#define UUID_DEVICE_LABELING "e5c937d0-3553-4d7a-9117-ea4d19c3434d"
|
||||
#define UUID_PHYSICAL_PRESENCE "3dddfaa6-361b-4eb4-a424-8d10089d1653"
|
||||
|
||||
/* TPM */
|
||||
#define UUID_HARDWARE_INFORMATION "cf8e16a5-c1e8-4e25-b712-4f54a96702c8"
|
||||
#define UUID_START_METHOD "6bbf6cab-5463-4714-b7cd-f0203c0368d4"
|
||||
#define UUID_MEMORY_CLEAR "376054ed-cc13-4675-901c-4756d7f2d45d"
|
||||
|
||||
/* NVDIMM - NFIT table */
|
||||
|
||||
#define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
|
||||
@@ -71,4 +76,5 @@
|
||||
#define UUID_USB4_CAPABILITIES "23a0d13a-26ab-486c-9c5f-0ffa525a575a"
|
||||
#define UUID_1ST_FUNCTION_ID "893f00a6-660c-494e-bcfd-3043f4fb67c0"
|
||||
#define UUID_2ND_FUNCTION_ID "107ededd-d381-4fd7-8da9-08e9a6c79644"
|
||||
#define UUID_FAN_TRIP_POINTS "a7611840-99fe-41ae-a488-35c75926c8eb"
|
||||
#endif /* __ACUUID_H__ */
|
||||
|
||||
Reference in New Issue
Block a user