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Merge tag 'amlogic-dt64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

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Pull "Amlogic 64-bit DT updates for v4.16" from Kevin Hilman
- meson-gx: add VPU power domain support
- odroid-c2: add HDMI and CEC nodes
- misc cleanups

* tag 'amlogic-dt64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: meson-gxm: fix q200 interrupt number
  ARM64: dts: meson-gxm: add the PHY interrupt line on Khadas VIM2
  ARM64: dts: meson: add comments with the GPIO for the PHY interrupts
  ARM64: dts: amlogic: use generic bus node names
  ARM64: dts: meson: drop "sana" clock from SAR ADC
  ARM64: dts: odroid-c2: Add HDMI and CEC Nodes
  ARM64: dts: meson-gx: grow reset controller memory zone
  ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards
  ARM64: dts: meson-gx: add VPU power domain
This commit is contained in:
Arnd Bergmann
2017-12-21 16:38:31 +01:00
parent c4e8db5f05 3106507e10
commit 8d7ac420c1
12 changed files with 192 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@@ -113,7 +113,7 @@ soc {
#size-cells = <2>;
ranges;
cbus: cbus@ffd00000 {
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
@@ -175,7 +175,7 @@ cpu_scp_hpri: scp-shmem@200 {
};
};
aobus: aobus@ff800000 {
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
#address-cells = <2>;

12
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@@ -59,6 +59,18 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
hdmi_5v: regulator-hdmi-5v {
compatible = "regulator-fixed";
regulator-name = "HDMI_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";

19
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@@ -211,7 +211,7 @@ soc {
#size-cells = <2>;
ranges;
cbus: cbus@c1100000 {
cbus: bus@c1100000 {
compatible = "simple-bus";
reg = <0x0 0xc1100000 0x0 0x100000>;
#address-cells = <2>;
@@ -229,7 +229,7 @@ gpio_intc: interrupt-controller@9880 {
reset: reset-controller@4404 {
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
reg = <0x0 0x04404 0x0 0x9c>;
#reset-cells = <1>;
};
@@ -366,7 +366,7 @@ cpu_scp_hpri: scp-shmem@200 {
};
};
aobus: aobus@c8100000 {
aobus: bus@c8100000 {
compatible = "simple-bus";
reg = <0x0 0xc8100000 0x0 0x100000>;
#address-cells = <2>;
@@ -377,6 +377,12 @@ sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
reg = <0x0 0x0 0x0 0x100>;
pwrc_vpu: power-controller-vpu {
compatible = "amlogic,meson-gx-pwrc-vpu";
#power-domain-cells = <0>;
amlogic,hhi-sysctrl = <&sysctrl>;
};
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
@@ -447,13 +453,18 @@ hwrng: rng {
};
};
hiubus: hiubus@c883c000 {
hiubus: bus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
};
mailbox: mailbox@404 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
View File

@@ -169,6 +169,7 @@ eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};

32
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@@ -135,6 +135,24 @@ emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&cec_AO {
status = "okay";
pinctrl-0 = <&ao_cec_pins>;
pinctrl-names = "default";
hdmi-phandle = <&hdmi_tx>;
};
&ethmac {
@@ -156,8 +174,10 @@ mdio {
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
};
@@ -179,6 +199,18 @@ usb-hub {
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
View File

@@ -118,6 +118,7 @@ eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};

46
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@@ -694,14 +694,55 @@ mux {
};
};
&pwrc_vpu {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_BT656>,
<&reset RESET_DVIN_RESET>,
<&reset RESET_RDMA>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC>,
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
&saradc {
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
clock-names = "clkin", "core", "adc_clk", "adc_sel";
};
&sd_emmc_a {
@@ -763,4 +804,5 @@ &uart_C {
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
power-domains = <&pwrc_vpu>;
};

12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@@ -72,6 +72,18 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
hdmi_5v: regulator-hdmi-5v {
compatible = "regulator-fixed";
regulator-name = "HDMI_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";

12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
View File

@@ -28,6 +28,18 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
hdmi_5v: regulator-hdmi-5v {
compatible = "regulator-fixed";
regulator-name = "HDMI_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";

46
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@@ -644,14 +644,55 @@ external_mdio: mdio@2009087f {
};
};
&pwrc_vpu {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
<&reset RESET_BT656>,
<&reset RESET_DVIN_RESET>,
<&reset RESET_RDMA>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC>,
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
/*
* VPU clocking is provided by two identical clock paths
* VPU_0 and VPU_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
* Same for VAPB but with a final gate after the glitch free mux.
*/
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
<&clkc CLKID_VPU_0>,
<&clkc CLKID_VPU>, /* Glitch free mux */
<&clkc CLKID_VAPB_0_SEL>,
<&clkc CLKID_VAPB_0>,
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_VPU_0>,
<&clkc CLKID_FCLK_DIV4>,
<0>, /* Do Nothing */
<&clkc CLKID_VAPB_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>, /* Do Nothing */
<0>, /* Do Nothing */
<250000000>,
<0>; /* Do Nothing */
};
&saradc {
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
clocks = <&xtal>,
<&clkc CLKID_SAR_ADC>,
<&clkc CLKID_SANA>,
<&clkc CLKID_SAR_ADC_CLK>,
<&clkc CLKID_SAR_ADC_SEL>;
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
clock-names = "clkin", "core", "adc_clk", "adc_sel";
};
&sd_emmc_a {
@@ -713,4 +754,5 @@ &uart_C {
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
power-domains = <&pwrc_vpu>;
};

15
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
View File

@@ -153,6 +153,18 @@ map3 {
};
};
hdmi_5v: regulator-hdmi-5v {
compatible = "regulator-fixed";
regulator-name = "HDMI_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
@@ -232,6 +244,9 @@ &external_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
};
};

3
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
View File

@@ -111,7 +111,8 @@ external_phy: ethernet-phy@0 {
reg = <0>;
max-speed = <1000>;
interrupt-parent = <&gpio_intc>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
/* MAC_INTR on GPIOZ_15 */
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
};
};