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clk: renesas: r9a06g032: Add restart handler

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The SYSCTRL module also does reset handling. Start supporting that by
allowing software resets which can then be utilized by a restart
handler. Finally 'reboot' will do something useful on RZ/N1D. Watchdog
support to be added later.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241128091113.24116-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Wolfram Sang
2024-11-28 10:11:11 +01:00
committed by Geert Uytterhoeven
parent b73435047e
commit 8b69ca3960
1 changed files with 27 additions and 0 deletions
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27
drivers/clk/renesas/r9a06g032-clocks.c
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@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/soc/renesas/r9a06g032-sysctrl.h>
#include <linux/spinlock.h>
@@ -29,6 +30,14 @@
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
#define R9A06G032_SYSCTRL_RSTEN 0x120
#define R9A06G032_SYSCTRL_RSTEN_MRESET_EN BIT(0)
#define R9A06G032_SYSCTRL_RSTCTRL 0x198
/* These work for both reset registers */
#define R9A06G032_SYSCTRL_SWRST BIT(6)
#define R9A06G032_SYSCTRL_WDA7RST_1 BIT(2)
#define R9A06G032_SYSCTRL_WDA7RST_0 BIT(1)
/**
* struct regbit - describe one bit in a register
* @reg: offset of register relative to base address,
@@ -1270,6 +1279,12 @@ static void r9a06g032_clocks_del_clk_provider(void *data)
of_clk_del_provider(data);
}
static int r9a06g032_restart_handler(struct sys_off_data *data)
{
writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);
return NOTIFY_DONE;
}
static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
{
struct device_node *usbf_np;
@@ -1324,6 +1339,18 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
r9a06g032_init_h2mode(clocks);
/* Clear potentially pending resets */
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
/* Allow software reset */
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
r9a06g032_restart_handler, NULL);
if (error)
dev_warn(dev, "couldn't register restart handler (%d)\n", error);
for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
const char *parent_name = d->source ?