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arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock

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The RZ/G3E SMARC SoM has a fixed 100 MHz reference clock generator
for PCIe.  Model it as a fixed-clock and assign it to the PCIe port.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260318085119.44717-4-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
John Madieu
2026-03-18 09:51:18 +01:00
committed by Geert Uytterhoeven
parent 1ac57c9830
commit 8af9fd59cb
1 changed files with 11 additions and 0 deletions
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11
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
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@@ -43,6 +43,12 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0xf8000000>;
};
pcie_refclk: pcie-ref-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -174,6 +180,11 @@ phy1: ethernet-phy@7 {
};
};
&pcie_port0 {
clocks = <&pcie_refclk>;
clock-names = "ref";
};
&pinctrl {
eth0_pins: eth0 {
clk {