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drm/msm/dsi: simplify vco_delay handling in dsi_phy_28nm driver

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Instead of setting the variable and then using it just in the one place,
determine vco_delay directly at the PLL configuration time.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-16-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Dmitry Baryshkov
2021-03-31 13:57:26 +03:00
committed by Rob Clark
parent 015cf32983
commit 89da81530d
1 changed files with 4 additions and 8 deletions
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12
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
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@@ -72,8 +72,6 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
int vco_delay;
struct pll_28nm_cached_state cached_state;
};
@@ -212,8 +210,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
/* Add hardware recommended delay for correct PLL configuration */
if (pll_28nm->vco_delay)
udelay(pll_28nm->vco_delay);
if (pll->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
udelay(1000);
else
udelay(1);
pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
@@ -580,10 +580,6 @@ static int dsi_pll_28nm_init(struct msm_dsi_phy *phy)
pll = &pll_28nm->base;
pll->cfg = phy->cfg;
if (phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP)
pll_28nm->vco_delay = 1000;
else
pll_28nm->vco_delay = 1;
ret = pll_28nm_register(pll_28nm, phy->provided_clocks->hws);
if (ret) {