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synced 2026-07-22 02:17:36 -04:00
EDAC/{skx_common,i10nm}: Move RRL handling to common code
Move RRL (Retry Read error Log) handling from i10nm_edac to skx_common so it can be shared across EDAC drivers (e.g. imh_edac). - Move RRL enable/disable and log dumping helpers to skx_common to avoid code duplication and enable reuse by other drivers. - Export skx_enable_rrl() and skx_show_rrl() so common RRL handling can be used by i10nm_edac and imh_edac. No functional change intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-6-qiuxu.zhuo@intel.com
This commit is contained in:
Qiuxu Zhuo
@@ -183,191 +183,6 @@ static struct reg_rrl gnr_reg_rrl_ddr = {
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.cecnt_widths = {4, 4, 4, 4, 4, 4, 4, 4},
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};
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static void enable_rrl(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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int rrl_set, bool enable, u32 *rrl_ctl)
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{
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enum rrl_source_type source = rrl->sources[rrl_set];
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u32 offset = rrl->offsets[rrl_set][0], v;
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u8 width = rrl->widths[0];
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bool first, scrub;
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/* First or last read error. */
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first = (source == RRL_SRC_FRE_SCRUB || source == RRL_SRC_FRE_DEMAND);
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/* Patrol scrub or on-demand read error. */
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scrub = (source == RRL_SRC_FRE_SCRUB || source == RRL_SRC_LRE_SCRUB);
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v = skx_read_imc_reg(imc, chan, offset, width);
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if (enable) {
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/* Save default configurations. */
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*rrl_ctl = v;
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v &= ~rrl->uc_mask;
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if (first)
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v |= rrl->noover_mask;
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else
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v &= ~rrl->noover_mask;
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if (scrub)
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v |= rrl->en_patspr_mask;
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else
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v &= ~rrl->en_patspr_mask;
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v |= rrl->en_mask;
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} else {
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/* Restore default configurations. */
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if (*rrl_ctl & rrl->uc_mask)
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v |= rrl->uc_mask;
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if (first) {
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if (!(*rrl_ctl & rrl->noover_mask))
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v &= ~rrl->noover_mask;
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} else {
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if (*rrl_ctl & rrl->noover_mask)
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v |= rrl->noover_mask;
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}
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if (scrub) {
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if (!(*rrl_ctl & rrl->en_patspr_mask))
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v &= ~rrl->en_patspr_mask;
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} else {
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if (*rrl_ctl & rrl->en_patspr_mask)
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v |= rrl->en_patspr_mask;
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}
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if (!(*rrl_ctl & rrl->en_mask))
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v &= ~rrl->en_mask;
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}
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skx_write_imc_reg(imc, chan, offset, width, v);
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}
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static void enable_rrls(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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bool enable, u32 *rrl_ctl)
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{
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for (int i = 0; i < rrl->set_num; i++)
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enable_rrl(imc, chan, rrl, i, enable, rrl_ctl + i);
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}
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static void enable_rrls_ddr(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl *rrl_ddr = res_cfg->reg_rrl_ddr;
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int i, chan_num = res_cfg->ddr_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase)
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return;
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for (i = 0; i < chan_num; i++)
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enable_rrls(imc, i, rrl_ddr, enable, chan[i].rrl_ctl[0]);
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}
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static void enable_rrls_hbm(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl **rrl_hbm = res_cfg->reg_rrl_hbm;
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int i, chan_num = res_cfg->hbm_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase || !imc->hbm_mc || !rrl_hbm[0] || !rrl_hbm[1])
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return;
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for (i = 0; i < chan_num; i++) {
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enable_rrls(imc, i, rrl_hbm[0], enable, chan[i].rrl_ctl[0]);
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enable_rrls(imc, i, rrl_hbm[1], enable, chan[i].rrl_ctl[1]);
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}
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}
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static void enable_retry_rd_err_log(bool enable)
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{
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struct skx_dev *d;
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int i, imc_num;
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edac_dbg(2, "\n");
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list_for_each_entry(d, i10nm_edac_list, list) {
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imc_num = res_cfg->ddr_imc_num;
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for (i = 0; i < imc_num; i++)
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enable_rrls_ddr(&d->imc[i], enable);
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imc_num += res_cfg->hbm_imc_num;
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for (; i < imc_num; i++)
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enable_rrls_hbm(&d->imc[i], enable);
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}
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}
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static void show_retry_rd_err_log(struct decoded_addr *res, char *msg,
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int len, bool scrub_err)
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{
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int i, j, n, ch = res->channel, pch = res->cs & 1;
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struct skx_imc *imc = &res->dev->imc[res->imc];
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u64 log, corr, status_mask;
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struct reg_rrl *rrl;
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bool scrub;
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u32 offset;
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u8 width;
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if (!imc->mbase)
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return;
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rrl = imc->hbm_mc ? res_cfg->reg_rrl_hbm[pch] : res_cfg->reg_rrl_ddr;
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if (!rrl)
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return;
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status_mask = rrl->over_mask | rrl->uc_mask | rrl->v_mask;
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n = scnprintf(msg, len, " retry_rd_err_log[");
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for (i = 0; i < rrl->set_num; i++) {
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scrub = (rrl->sources[i] == RRL_SRC_FRE_SCRUB || rrl->sources[i] == RRL_SRC_LRE_SCRUB);
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if (scrub_err != scrub)
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continue;
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for (j = 0; j < rrl->reg_num && len - n > 0; j++) {
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offset = rrl->offsets[i][j];
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width = rrl->widths[j];
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log = skx_read_imc_reg(imc, ch, offset, width);
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if (width == 4)
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n += scnprintf(msg + n, len - n, "%.8llx ", log);
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else
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n += scnprintf(msg + n, len - n, "%.16llx ", log);
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/* Clear RRL status if RRL in Linux control mode. */
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if (res_cfg->rrl_ctrl_mode == RRL_CTRL_LINUX && !j && (log & status_mask))
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skx_write_imc_reg(imc, ch, offset, width, log & ~status_mask);
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}
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}
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/* Move back one space. */
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n--;
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n += scnprintf(msg + n, len - n, "]");
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if (len - n > 0) {
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n += scnprintf(msg + n, len - n, " correrrcnt[");
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for (i = 0; i < rrl->cecnt_num && len - n > 0; i++) {
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offset = rrl->cecnt_offsets[i];
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width = rrl->cecnt_widths[i];
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corr = skx_read_imc_reg(imc, ch, offset, width);
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/* CPUs {ICX,SPR} encode two counters per 4-byte CORRERRCNT register. */
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if (res_cfg->type <= SPR) {
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n += scnprintf(msg + n, len - n, "%.4llx %.4llx ",
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corr & 0xffff, corr >> 16);
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} else {
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/* CPUs {GNR} encode one counter per CORRERRCNT register. */
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if (width == 4)
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n += scnprintf(msg + n, len - n, "%.8llx ", corr);
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else
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n += scnprintf(msg + n, len - n, "%.16llx ", corr);
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}
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}
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/* Move back one space. */
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n--;
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n += scnprintf(msg + n, len - n, "]");
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}
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}
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static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
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unsigned int dev, unsigned int fun)
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{
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@@ -1209,9 +1024,9 @@ static int __init i10nm_init(void)
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res_cfg->rrl_ctrl_mode = retry_rd_err_log;
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if (retry_rd_err_log && res_cfg->reg_rrl_ddr) {
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skx_set_show_rrl(show_retry_rd_err_log);
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skx_set_show_rrl(skx_show_rrl);
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if (retry_rd_err_log == RRL_CTRL_LINUX)
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enable_retry_rd_err_log(true);
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skx_enable_rrl(true);
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}
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skx_set_decode(i10nm_mc_decode);
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@@ -1232,7 +1047,7 @@ static void __exit i10nm_exit(void)
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if (retry_rd_err_log && res_cfg->reg_rrl_ddr) {
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if (retry_rd_err_log == RRL_CTRL_LINUX)
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enable_retry_rd_err_log(false);
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skx_enable_rrl(false);
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skx_set_show_rrl(NULL);
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}
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@@ -102,6 +102,192 @@ void skx_write_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width, u64
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}
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EXPORT_SYMBOL_GPL(skx_write_imc_reg);
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static void enable_rrl(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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int rrl_set, bool enable, u32 *rrl_ctl)
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{
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enum rrl_source_type source = rrl->sources[rrl_set];
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u32 offset = rrl->offsets[rrl_set][0], v;
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u8 width = rrl->widths[0];
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bool first, scrub;
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/* First or last read error. */
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first = (source == RRL_SRC_FRE_SCRUB || source == RRL_SRC_FRE_DEMAND);
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/* Patrol scrub or on-demand read error. */
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scrub = (source == RRL_SRC_FRE_SCRUB || source == RRL_SRC_LRE_SCRUB);
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v = skx_read_imc_reg(imc, chan, offset, width);
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if (enable) {
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/* Save default configurations. */
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*rrl_ctl = v;
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v &= ~rrl->uc_mask;
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if (first)
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v |= rrl->noover_mask;
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else
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v &= ~rrl->noover_mask;
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if (scrub)
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v |= rrl->en_patspr_mask;
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else
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v &= ~rrl->en_patspr_mask;
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v |= rrl->en_mask;
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} else {
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/* Restore default configurations. */
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if (*rrl_ctl & rrl->uc_mask)
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v |= rrl->uc_mask;
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if (first) {
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if (!(*rrl_ctl & rrl->noover_mask))
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v &= ~rrl->noover_mask;
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} else {
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if (*rrl_ctl & rrl->noover_mask)
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v |= rrl->noover_mask;
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}
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if (scrub) {
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if (!(*rrl_ctl & rrl->en_patspr_mask))
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v &= ~rrl->en_patspr_mask;
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} else {
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if (*rrl_ctl & rrl->en_patspr_mask)
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v |= rrl->en_patspr_mask;
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}
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if (!(*rrl_ctl & rrl->en_mask))
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v &= ~rrl->en_mask;
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}
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skx_write_imc_reg(imc, chan, offset, width, v);
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}
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static void enable_rrls(struct skx_imc *imc, int chan, struct reg_rrl *rrl,
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bool enable, u32 *rrl_ctl)
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{
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for (int i = 0; i < rrl->set_num; i++)
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enable_rrl(imc, chan, rrl, i, enable, rrl_ctl + i);
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}
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static void enable_rrls_ddr(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl *rrl_ddr = skx_res_cfg->reg_rrl_ddr;
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int i, chan_num = skx_res_cfg->ddr_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase)
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return;
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for (i = 0; i < chan_num; i++)
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enable_rrls(imc, i, rrl_ddr, enable, chan[i].rrl_ctl[0]);
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}
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static void enable_rrls_hbm(struct skx_imc *imc, bool enable)
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{
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struct reg_rrl **rrl_hbm = skx_res_cfg->reg_rrl_hbm;
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int i, chan_num = skx_res_cfg->hbm_chan_num;
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struct skx_channel *chan = imc->chan;
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if (!imc->mbase || !imc->hbm_mc || !rrl_hbm[0] || !rrl_hbm[1])
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return;
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for (i = 0; i < chan_num; i++) {
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enable_rrls(imc, i, rrl_hbm[0], enable, chan[i].rrl_ctl[0]);
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enable_rrls(imc, i, rrl_hbm[1], enable, chan[i].rrl_ctl[1]);
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}
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}
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void skx_enable_rrl(bool enable)
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{
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struct skx_dev *d;
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int i, imc_num;
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edac_dbg(2, "\n");
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list_for_each_entry(d, &dev_edac_list, list) {
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imc_num = skx_res_cfg->ddr_imc_num;
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for (i = 0; i < imc_num; i++)
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enable_rrls_ddr(&d->imc[i], enable);
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imc_num += skx_res_cfg->hbm_imc_num;
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for (; i < imc_num; i++)
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enable_rrls_hbm(&d->imc[i], enable);
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}
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}
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EXPORT_SYMBOL_GPL(skx_enable_rrl);
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void skx_show_rrl(struct decoded_addr *res, char *msg, int len, bool scrub_err)
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{
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int i, j, n, ch = res->channel, pch = res->cs & 1;
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struct skx_imc *imc = &res->dev->imc[res->imc];
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u64 log, corr, status_mask;
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struct reg_rrl *rrl;
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bool scrub;
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u32 offset;
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u8 width;
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if (!imc->mbase)
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return;
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rrl = imc->hbm_mc ? skx_res_cfg->reg_rrl_hbm[pch] : skx_res_cfg->reg_rrl_ddr;
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if (!rrl)
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return;
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status_mask = rrl->over_mask | rrl->uc_mask | rrl->v_mask;
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n = scnprintf(msg, len, " retry_rd_err_log[");
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for (i = 0; i < rrl->set_num; i++) {
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scrub = (rrl->sources[i] == RRL_SRC_FRE_SCRUB || rrl->sources[i] == RRL_SRC_LRE_SCRUB);
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if (scrub_err != scrub)
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continue;
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for (j = 0; j < rrl->reg_num && len - n > 0; j++) {
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offset = rrl->offsets[i][j];
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width = rrl->widths[j];
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log = skx_read_imc_reg(imc, ch, offset, width);
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if (width == 4)
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n += scnprintf(msg + n, len - n, "%.8llx ", log);
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else
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n += scnprintf(msg + n, len - n, "%.16llx ", log);
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/* Clear RRL status if RRL in Linux control mode. */
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if (skx_res_cfg->rrl_ctrl_mode == RRL_CTRL_LINUX && !j && (log & status_mask))
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skx_write_imc_reg(imc, ch, offset, width, log & ~status_mask);
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}
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}
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/* Move back one space. */
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n--;
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n += scnprintf(msg + n, len - n, "]");
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if (len - n > 0) {
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n += scnprintf(msg + n, len - n, " correrrcnt[");
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for (i = 0; i < rrl->cecnt_num && len - n > 0; i++) {
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offset = rrl->cecnt_offsets[i];
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width = rrl->cecnt_widths[i];
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corr = skx_read_imc_reg(imc, ch, offset, width);
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/* CPUs {ICX,SPR} encode two counters per 4-byte CORRERRCNT register. */
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if (skx_res_cfg->type <= SPR) {
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n += scnprintf(msg + n, len - n, "%.4llx %.4llx ",
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corr & 0xffff, corr >> 16);
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} else {
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/* CPUs {GNR} encode one counter per CORRERRCNT register. */
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if (width == 4)
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n += scnprintf(msg + n, len - n, "%.8llx ", corr);
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else
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n += scnprintf(msg + n, len - n, "%.16llx ", corr);
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}
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}
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/* Move back one space. */
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n--;
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n += scnprintf(msg + n, len - n, "]");
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}
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}
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EXPORT_SYMBOL_GPL(skx_show_rrl);
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int skx_adxl_get(void)
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{
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const char * const *names;
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@@ -344,6 +344,8 @@ int skx_adxl_get(void);
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void skx_adxl_put(void);
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void skx_set_decode(skx_decode_f decode);
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void skx_set_show_rrl(skx_show_rrl_f rrl);
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void skx_show_rrl(struct decoded_addr *res, char *msg, int len, bool scrub_err);
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void skx_enable_rrl(bool enable);
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void skx_set_mem_cfg(bool mem_cfg_2lm);
|
||||
void skx_set_res_cfg(struct res_config *cfg);
|
||||
void skx_init_mc_mapping(struct skx_dev *d);
|
||||
|
||||
Reference in New Issue
Block a user