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drm/amdgpu: Correct xcc_id input to GET_INST from physical to logic

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Correct xcc_id input to GET_INST from physical to logic for
gfx_v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
2025-07-02 13:09:22 +08:00
committed by Alex Deucher
parent a056771b30
commit 89745c19c6
3 changed files with 24 additions and 37 deletions
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6
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
View File

@@ -1935,7 +1935,7 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad
}
memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
for_each_inst(xcc_id, xcc_mask) {
for (xcc_id = 0; xcc_id < NUM_XCC(xcc_mask); xcc_id++) {
for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) *
ALIGN(fw_data_size, 64 * 1024) / 4;
@@ -1948,7 +1948,7 @@ static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *ad
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
for_each_inst(xcc_id, xcc_mask) {
for (xcc_id = 0; xcc_id < NUM_XCC(xcc_mask); xcc_id++) {
gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id);
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL);
@@ -2431,7 +2431,7 @@ static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask
return r;
}
for_each_inst(xcc_id, xcc_mask) {
for (xcc_id = 0; xcc_id < NUM_XCC(xcc_mask); xcc_id++) {
if (!(adev->flags & AMD_IS_APU))
gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);

53
drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c
View File

@@ -65,7 +65,7 @@ static void gfxhub_v12_1_xcc_setup_vm_pt_regs(struct amdgpu_device *adev,
struct amdgpu_vmhub *hub;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
@@ -83,10 +83,8 @@ static void gfxhub_v12_1_setup_vm_pt_regs(struct amdgpu_device *adev,
uint32_t vmid,
uint64_t page_table_base)
{
uint32_t xcc_mask;
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask);
gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base,
adev->gfx.xcc_mask);
}
static void gfxhub_v12_1_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,
@@ -105,7 +103,7 @@ static void gfxhub_v12_1_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,
/* If use GART for FB translation, vmid0 page table covers both
* vram and system memory (gart)
*/
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
if (adev->gmc.pdb0_bo) {
WREG32_SOC15(GC, GET_INST(GC, i),
regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
@@ -145,7 +143,7 @@ static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *ade
uint32_t tmp;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
/* Program the AGP BAR */
WREG32_SOC15_RLC(GC, GET_INST(GC, i),
regGCMC_VM_AGP_BASE_LO32, 0);
@@ -247,7 +245,7 @@ static void gfxhub_v12_1_xcc_init_tlb_regs(struct amdgpu_device *adev,
uint32_t tmp;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
/* Setup TLB control */
tmp = RREG32_SOC15(GC, GET_INST(GC, i),
regGCMC_VM_MX_L1_TLB_CNTL);
@@ -282,7 +280,7 @@ static void gfxhub_v12_1_xcc_init_cache_regs(struct amdgpu_device *adev,
uint32_t tmp;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
/* Setup L2 cache */
tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
@@ -343,7 +341,7 @@ static void gfxhub_v12_1_xcc_enable_system_domain(struct amdgpu_device *adev,
uint32_t tmp;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
tmp = RREG32_SOC15(GC, GET_INST(GC, i),
regGCVM_CONTEXT0_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
@@ -366,7 +364,7 @@ static void gfxhub_v12_1_xcc_disable_identity_aperture(struct amdgpu_device *ade
{
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
WREG32_SOC15(GC, GET_INST(GC, i),
regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0XFFFFFFFF);
@@ -402,7 +400,7 @@ static void gfxhub_v12_1_xcc_setup_vmid_config(struct amdgpu_device *adev,
block_size = adev->vm_manager.block_size;
block_size -= 9;
for_each_inst(j, xcc_mask) {
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
@@ -460,7 +458,7 @@ static void gfxhub_v12_1_xcc_program_invalidation(struct amdgpu_device *adev,
struct amdgpu_vmhub *hub;
unsigned int i, j;
for_each_inst(j, xcc_mask) {
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
for (i = 0 ; i < 18; ++i) {
@@ -483,7 +481,7 @@ static int gfxhub_v12_1_xcc_gart_enable(struct amdgpu_device *adev,
/* GCMC_VM_FB_LOCATION_BASE/TOP are VF copy registers
* VBIO post does not program them at boot up phase
* Need driver to program them from guest side */
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
WREG32_SOC15(GC, GET_INST(GC, i),
regGCMC_VM_FB_LOCATION_BASE_LO32,
lower_32_bits(adev->gmc.vram_start >> 24));
@@ -516,10 +514,8 @@ static int gfxhub_v12_1_xcc_gart_enable(struct amdgpu_device *adev,
static int gfxhub_v12_1_gart_enable(struct amdgpu_device *adev)
{
uint32_t xcc_mask;
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
return gfxhub_v12_1_xcc_gart_enable(adev, xcc_mask);
return gfxhub_v12_1_xcc_gart_enable(adev,
adev->gfx.xcc_mask);
}
static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev,
@@ -529,7 +525,7 @@ static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev,
u32 tmp;
u32 i, j;
for_each_inst(j, xcc_mask) {
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
/* Disable all tables */
for (i = 0; i < 16; i++)
@@ -559,10 +555,7 @@ static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev,
static void gfxhub_v12_1_gart_disable(struct amdgpu_device *adev)
{
uint32_t xcc_mask;
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
gfxhub_v12_1_xcc_gart_disable(adev, xcc_mask);
gfxhub_v12_1_xcc_gart_disable(adev, adev->gfx.xcc_mask);
}
static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev,
@@ -571,7 +564,7 @@ static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev
u32 tmp;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
tmp = RREG32_SOC15(GC, GET_INST(GC, i),
regGCVM_L2_PROTECTION_FAULT_CNTL_LO32);
tmp = REG_SET_FIELD(tmp,
@@ -644,10 +637,7 @@ static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev
static void gfxhub_v12_1_set_fault_enable_default(struct amdgpu_device *adev,
bool value)
{
uint32_t xcc_mask;
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, xcc_mask);
gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, adev->gfx.xcc_mask);
}
static uint32_t gfxhub_v12_1_get_invalidate_req(unsigned int vmid,
@@ -744,7 +734,7 @@ static void gfxhub_v12_1_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
struct amdgpu_vmhub *hub;
int i;
for_each_inst(i, xcc_mask) {
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
hub->ctx0_ptb_addr_lo32 =
@@ -800,10 +790,7 @@ static void gfxhub_v12_1_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
static void gfxhub_v12_1_init(struct amdgpu_device *adev)
{
uint32_t xcc_mask;
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
gfxhub_v12_1_xcc_init(adev, xcc_mask);
gfxhub_v12_1_xcc_init(adev, adev->gfx.xcc_mask);
}
static int gfxhub_v12_1_get_xgmi_info(struct amdgpu_device *adev)

2
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
View File

@@ -319,7 +319,7 @@ static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
1 << vmid, GET_INST(GC, 0));
1 << vmid, 0);
return;
}