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drm/amd/display: Use pixels per container logic for DCN314 DCCG dividers
[Why] DP DSC YCbCr422 not working because dcn314_calculate_dccg_k1_k2_values does not account for two pixels per container [How] Replace the contents of dcn314_calculate_dccg_k1_k2_values with the code from the function dcn32_calculate_dccg_k1_k2_values Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Daniel Miess <Daniel.Miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
1ff77beac8
commit
89390c4982
@@ -343,7 +343,10 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
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{
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struct dc_stream_state *stream = pipe_ctx->stream;
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unsigned int odm_combine_factor = 0;
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struct dc *dc = pipe_ctx->stream->ctx->dc;
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bool two_pix_per_container = false;
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two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
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odm_combine_factor = get_odm_config(pipe_ctx, NULL);
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if (is_dp_128b_132b_signal(pipe_ctx)) {
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@@ -355,16 +358,13 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
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else
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*k2_div = PIXEL_RATE_DIV_BY_4;
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} else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
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if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
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if (two_pix_per_container) {
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*k1_div = PIXEL_RATE_DIV_BY_1;
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*k2_div = PIXEL_RATE_DIV_BY_2;
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} else if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
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*k1_div = PIXEL_RATE_DIV_BY_2;
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*k2_div = PIXEL_RATE_DIV_BY_2;
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} else {
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if (odm_combine_factor == 1)
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*k2_div = PIXEL_RATE_DIV_BY_4;
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else if (odm_combine_factor == 2)
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*k1_div = PIXEL_RATE_DIV_BY_1;
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*k2_div = PIXEL_RATE_DIV_BY_4;
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if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)
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*k2_div = PIXEL_RATE_DIV_BY_2;
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}
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}
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