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Merge tag 'mvebu-dt64-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt

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mvebu dt64 for 6.19 (part 1)

pinctrl node names cleanup from Rob on Marvell device tree files
Proper fix for pci errors on armada cp11x based platforms

* tag 'mvebu-dt64-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  clk: mvebu: cp110 add CLK_IGNORE_UNUSED to pcie_x10, pcie_x11 & pcie_x4
  Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports"
  arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node names

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 21:05:33 +01:00
parent 314bfe59ec f0e6bc0c3e
commit 887bc88163
7 changed files with 27 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/marvell/armada-38x.dtsi
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@@ -247,7 +247,7 @@ nand_pins: nand-pins {
marvell,function = "dev";
};
nand_rb: nand-rb {
nand_rb: nand-rb-pins {
marvell,pins = "mpp41";
marvell,function = "nand";
};

2
arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi
View File

@@ -322,7 +322,7 @@ nand_pins: nand-pins {
marvell,function = "dev";
};
nand_rb: nand-rb {
nand_rb: nand-rb-pins {
marvell,pins = "mpp19";
marvell,function = "nand";
};

2
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View File

@@ -56,7 +56,7 @@ nand_pins: nand-pins {
marvell,function = "dev";
};
nand_rb: nand-rb {
nand_rb: nand-rb-pins {
marvell,pins = "mpp13";
marvell,function = "nf";
};

2
arch/arm64/boot/dts/marvell/armada-80x0.dtsi
View File

@@ -89,7 +89,7 @@ nand_pins: nand-pins {
marvell,function = "dev";
};
nand_rb: nand-rb {
nand_rb: nand-rb-pins {
marvell,pins = "mpp13", "mpp12";
marvell,function = "nf";
};

2
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
View File

@@ -379,7 +379,7 @@ nand_pins: nand-pins {
"mpp27";
marvell,function = "dev";
};
nand_rb: nand-rb {
nand_rb: nand-rb-pins {
marvell,pins = "mpp13";
marvell,function = "nf";
};

16
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
View File

@@ -413,13 +413,7 @@ fixed-link {
/* SRDS #0,#1,#2,#3 - PCIe */
&cp0_pcie0 {
num-lanes = <4>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
*/
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
status = "okay";
};
@@ -481,13 +475,7 @@ &cp1_eth0 {
/* SRDS #0,#1 - PCIe */
&cp1_pcie0 {
num-lanes = <2>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
*/
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
status = "okay";
};

20
drivers/clk/mvebu/cp110-system-controller.c
View File

@@ -110,6 +110,25 @@ static const char * const gate_base_names[] = {
[CP110_GATE_EIP197] = "eip197"
};
static unsigned long gate_flags(const u8 bit_idx)
{
switch (bit_idx) {
case CP110_GATE_PCIE_X1_0:
case CP110_GATE_PCIE_X1_1:
case CP110_GATE_PCIE_X4:
/*
* If a port had an active link at boot time, stopping
* the clock creates a failed state from which controller
* driver can not recover.
* Prevent stopping this clock till after a driver has taken
* ownership.
*/
return CLK_IGNORE_UNUSED;
default:
return 0;
}
};
struct cp110_gate_clk {
struct clk_hw hw;
struct regmap *regmap;
@@ -171,6 +190,7 @@ static struct clk_hw *cp110_register_gate(const char *name,
init.ops = &cp110_gate_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = gate_flags(bit_idx);
gate->regmap = regmap;
gate->bit_idx = bit_idx;