mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-09 12:33:18 -04:00
net: stmmac: remove pcs_get_adv_lp() support
It appears that the GMAC_ANE_ADV and GMAC_ANE_LPA registers are only
available for TBI and RTBI PHY interfaces. In commit 482b3c3ba7
("net: stmmac: Drop TBI/RTBI PCS flags") support for these was dropped,
and thus it no longer makes sense to access these registers.
Remove the *_get_adv_lp() functions, and the now redundant struct
rgmii_adv and STMMAC_PCS_* definitions.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://patch.msgid.link/E1uPkbT-004EyG-OQ@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
committed by
Jakub Kicinski
parent
3cfbde048b
commit
883af78926
@@ -396,17 +396,6 @@ enum request_irq_err {
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#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
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/* Physical Coding Sublayer */
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struct rgmii_adv {
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unsigned int pause;
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unsigned int duplex;
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unsigned int lp_pause;
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unsigned int lp_duplex;
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};
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#define STMMAC_PCS_PAUSE 1
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#define STMMAC_PCS_ASYM_PAUSE 2
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/* DMA HW capabilities */
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struct dma_features {
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unsigned int mbps_10_100;
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@@ -399,11 +399,6 @@ static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
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dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
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}
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static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
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{
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dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
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}
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static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
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struct stmmac_extra_stats *x,
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u32 rx_queues, u32 tx_queues)
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@@ -508,7 +503,6 @@ const struct stmmac_ops dwmac1000_ops = {
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.set_eee_pls = dwmac1000_set_eee_pls,
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.debug = dwmac1000_debug,
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.pcs_ctrl_ane = dwmac1000_ctrl_ane,
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.pcs_get_adv_lp = dwmac1000_get_adv_lp,
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.set_mac_loopback = dwmac1000_set_mac_loopback,
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};
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@@ -589,11 +589,6 @@ static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
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dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
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}
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static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
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{
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dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
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}
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/* RGMII or SMII interface */
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static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
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{
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@@ -958,7 +953,6 @@ const struct stmmac_ops dwmac4_ops = {
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.set_eee_timer = dwmac4_set_eee_timer,
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.set_eee_pls = dwmac4_set_eee_pls,
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.pcs_ctrl_ane = dwmac4_ctrl_ane,
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.pcs_get_adv_lp = dwmac4_get_adv_lp,
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.debug = dwmac4_debug,
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.set_filter = dwmac4_set_filter,
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.set_mac_loopback = dwmac4_set_mac_loopback,
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@@ -993,7 +987,6 @@ const struct stmmac_ops dwmac410_ops = {
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.set_eee_timer = dwmac4_set_eee_timer,
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.set_eee_pls = dwmac4_set_eee_pls,
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.pcs_ctrl_ane = dwmac4_ctrl_ane,
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.pcs_get_adv_lp = dwmac4_get_adv_lp,
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.debug = dwmac4_debug,
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.set_filter = dwmac4_set_filter,
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.flex_pps_config = dwmac5_flex_pps_config,
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@@ -1030,7 +1023,6 @@ const struct stmmac_ops dwmac510_ops = {
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.set_eee_timer = dwmac4_set_eee_timer,
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.set_eee_pls = dwmac4_set_eee_pls,
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.pcs_ctrl_ane = dwmac4_ctrl_ane,
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.pcs_get_adv_lp = dwmac4_get_adv_lp,
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.debug = dwmac4_debug,
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.set_filter = dwmac4_set_filter,
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.safety_feat_config = dwmac5_safety_feat_config,
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@@ -300,7 +300,6 @@ struct stmmac_dma_ops {
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struct mac_device_info;
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struct net_device;
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struct rgmii_adv;
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struct stmmac_tc_entry;
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struct stmmac_pps_cfg;
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struct stmmac_rss;
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@@ -377,7 +376,6 @@ struct stmmac_ops {
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/* PCS calls */
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void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
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bool loopback);
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void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
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/* Safety Features */
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int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp,
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struct stmmac_safety_feature_cfg *safety_cfg);
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@@ -467,8 +465,6 @@ struct stmmac_ops {
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stmmac_do_void_callback(__priv, mac, debug, __priv, __args)
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#define stmmac_pcs_ctrl_ane(__priv, __args...) \
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stmmac_do_void_callback(__priv, mac, pcs_ctrl_ane, __args)
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#define stmmac_pcs_get_adv_lp(__priv, __args...) \
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stmmac_do_void_callback(__priv, mac, pcs_get_adv_lp, __args)
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#define stmmac_safety_feat_config(__priv, __args...) \
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stmmac_do_callback(__priv, mac, safety_feat_config, __args)
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#define stmmac_safety_feat_irq_status(__priv, __args...) \
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@@ -325,7 +325,6 @@ static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
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if (!(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS) &&
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(priv->hw->pcs & STMMAC_PCS_RGMII ||
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priv->hw->pcs & STMMAC_PCS_SGMII)) {
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struct rgmii_adv adv;
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u32 supported, advertising, lp_advertising;
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if (!priv->xstats.pcs_link) {
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@@ -337,10 +336,6 @@ static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
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cmd->base.speed = priv->xstats.pcs_speed;
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/* Get and convert ADV/LP_ADV from the HW AN registers */
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if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
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return -EOPNOTSUPP; /* should never happen indeed */
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/* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
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ethtool_convert_link_mode_to_legacy_u32(
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@@ -350,44 +345,12 @@ static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
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ethtool_convert_link_mode_to_legacy_u32(
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&lp_advertising, cmd->link_modes.lp_advertising);
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if (adv.pause & STMMAC_PCS_PAUSE)
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advertising |= ADVERTISED_Pause;
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if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
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advertising |= ADVERTISED_Asym_Pause;
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if (adv.lp_pause & STMMAC_PCS_PAUSE)
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lp_advertising |= ADVERTISED_Pause;
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if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
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lp_advertising |= ADVERTISED_Asym_Pause;
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/* Reg49[3] always set because ANE is always supported */
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cmd->base.autoneg = ADVERTISED_Autoneg;
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supported |= SUPPORTED_Autoneg;
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advertising |= ADVERTISED_Autoneg;
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lp_advertising |= ADVERTISED_Autoneg;
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if (adv.duplex) {
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supported |= (SUPPORTED_1000baseT_Full |
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SUPPORTED_100baseT_Full |
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SUPPORTED_10baseT_Full);
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advertising |= (ADVERTISED_1000baseT_Full |
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ADVERTISED_100baseT_Full |
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ADVERTISED_10baseT_Full);
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} else {
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supported |= (SUPPORTED_1000baseT_Half |
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SUPPORTED_100baseT_Half |
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SUPPORTED_10baseT_Half);
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advertising |= (ADVERTISED_1000baseT_Half |
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ADVERTISED_100baseT_Half |
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ADVERTISED_10baseT_Half);
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}
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if (adv.lp_duplex)
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lp_advertising |= (ADVERTISED_1000baseT_Full |
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ADVERTISED_100baseT_Full |
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ADVERTISED_10baseT_Full);
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else
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lp_advertising |= (ADVERTISED_1000baseT_Half |
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ADVERTISED_100baseT_Half |
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ADVERTISED_10baseT_Half);
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cmd->base.port = PORT_OTHER;
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ethtool_convert_legacy_u32_to_link_mode(
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@@ -515,12 +478,9 @@ stmmac_get_pauseparam(struct net_device *netdev,
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struct ethtool_pauseparam *pause)
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{
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struct stmmac_priv *priv = netdev_priv(netdev);
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struct rgmii_adv adv_lp;
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if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
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if (priv->hw->pcs) {
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pause->autoneg = 1;
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if (!adv_lp.pause)
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return;
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} else {
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phylink_ethtool_get_pauseparam(priv->phylink, pause);
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}
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@@ -531,12 +491,9 @@ stmmac_set_pauseparam(struct net_device *netdev,
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struct ethtool_pauseparam *pause)
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{
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struct stmmac_priv *priv = netdev_priv(netdev);
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struct rgmii_adv adv_lp;
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if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
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if (priv->hw->pcs) {
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pause->autoneg = 1;
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if (!adv_lp.pause)
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return -EOPNOTSUPP;
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return 0;
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} else {
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return phylink_ethtool_set_pauseparam(priv->phylink, pause);
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@@ -16,6 +16,8 @@
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/* PCS registers (AN/TBI/SGMII/RGMII) offsets */
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#define GMAC_AN_CTRL(x) (x) /* AN control */
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#define GMAC_AN_STATUS(x) (x + 0x4) /* AN status */
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/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
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#define GMAC_ANE_ADV(x) (x + 0x8) /* ANE Advertisement */
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#define GMAC_ANE_LPA(x) (x + 0xc) /* ANE link partener ability */
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#define GMAC_ANE_EXP(x) (x + 0x10) /* ANE expansion */
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@@ -107,34 +109,4 @@ static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
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writel(value, ioaddr + GMAC_AN_CTRL(reg));
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}
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/**
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* dwmac_get_adv_lp - Get ADV and LP cap
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* @ioaddr: IO registers pointer
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* @reg: Base address of the AN Control Register.
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* @adv_lp: structure to store the adv,lp status
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* Description: this is to expose the ANE advertisement and Link partner ability
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* status to ethtool support.
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*/
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static inline void dwmac_get_adv_lp(void __iomem *ioaddr, u32 reg,
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struct rgmii_adv *adv_lp)
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{
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u32 value = readl(ioaddr + GMAC_ANE_ADV(reg));
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if (value & GMAC_ANE_FD)
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adv_lp->duplex = DUPLEX_FULL;
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if (value & GMAC_ANE_HD)
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adv_lp->duplex |= DUPLEX_HALF;
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adv_lp->pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
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value = readl(ioaddr + GMAC_ANE_LPA(reg));
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if (value & GMAC_ANE_FD)
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adv_lp->lp_duplex = DUPLEX_FULL;
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if (value & GMAC_ANE_HD)
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adv_lp->lp_duplex = DUPLEX_HALF;
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adv_lp->lp_pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
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}
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#endif /* __STMMAC_PCS_H__ */
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