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dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema
Convert Texas Instruments Keystone SoC Reset Controller from text to DT schema. no new functional changes. Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260813-ti-keystone-reset-v1-1-189389503324@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Bhargav Joshi
committed by
Rob Herring (Arm)
Rob Herring (Arm)
parent
3cb36d5626
commit
87aec8a16c
@@ -1,67 +0,0 @@
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* Device tree bindings for Texas Instruments keystone reset
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This node is intended to allow SoC reset in case of software reset
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of selected watchdogs.
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The Keystone SoCs can contain up to 4 watchdog timers to reset
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SoC. Each watchdog timer event input is connected to the Reset Mux
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block. The Reset Mux block can be configured to cause reset or not.
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Additionally soft or hard reset can be configured.
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Required properties:
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- compatible: ti,keystone-reset
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- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
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access pll controller registers and the offset to use
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reset control registers.
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- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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access device state control registers and the offset
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in order to use mux block registers for all watchdogs.
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Optional properties:
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- ti,soft-reset: Boolean option indicating soft reset.
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By default hard reset is used.
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- ti,wdt-list: WDT list that can cause SoC reset. It's not related
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to WDT driver, it's just needed to enable a SoC related
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reset that's triggered by one of WDTs. The list is
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in format: <0>, <2>; It can be in random order and
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begins from 0 to 3, as keystone can contain up to 4 SoC
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reset watchdogs and can be in random order.
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Example 1:
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Setup keystone reset so that in case software reset or
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WDT0 is triggered it issues hard reset for SoC.
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pllctrl: pll-controller@2310000 {
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compatible = "ti,keystone-pllctrl", "syscon";
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reg = <0x02310000 0x200>;
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};
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devctrl: device-state-control@2620000 {
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compatible = "ti,keystone-devctrl", "syscon";
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reg = <0x02620000 0x1000>;
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};
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>;
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};
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Example 2:
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Setup keystone reset so that in case of software reset or
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WDT0 or WDT2 is triggered it issues soft reset for SoC.
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>, <2>;
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ti,soft-reset;
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};
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@@ -0,0 +1,81 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/reset/ti,keystone-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI Keystone SoC Reset Controller
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maintainers:
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- Andrew Davis <afd@ti.com>
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description:
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This is intended to allow SoC reset in case of software reset of selected
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watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset
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SoC. Each watchdog timer event input is connected to the Reset Mux block. The
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Reset Mux block can be configured to cause reset or not. Additionally soft or
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hard reset can be configured.
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properties:
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compatible:
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const: ti,keystone-reset
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reg:
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maxItems: 1
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ti,syscon-pll:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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The phandle to syscon used to access pll controller registers and the
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offset to use reset control registers.
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items:
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- items:
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- description: phandle to pll controller syscon
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- description: offset within pll controller register space
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ti,syscon-dev:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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The phandle to syscon used to access device state control registers and
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the offset in order to use mux block registers for all watchdogs.
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items:
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- items:
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- description: phandle to device state control syscon
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- description: offset within device state control register
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ti,soft-reset:
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type: boolean
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description:
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Boolean option indicating soft reset. By default hard reset is used.
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ti,wdt-list:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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WDT list that can cause SoC reset. It's not related to WDT driver, it's
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just needed to enable a SoC related reset that's triggered by one of
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WDTs. The list is in format- <0>, <2>; It can be in random order and
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begins from 0 to 3, as keystone can contain up to 4 SoC reset watchdogs
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and can be in random order.
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minItems: 1
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maxItems: 4
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items:
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minimum: 0
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maximum: 3
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required:
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- compatible
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- reg
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- ti,syscon-pll
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- ti,syscon-dev
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additionalProperties: false
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examples:
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- |
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reset-controller@328 {
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compatible = "ti,keystone-reset";
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reg = <0x328 0x10>;
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>;
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};
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