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drm/amd/display: restyle dcn31 resource header inline with other asics

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Style change for better consistency across codebase

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2021-10-07 10:34:49 -04:00
committed by Alex Deucher
parent af9775a3e1
commit 876e835ed7
2 changed files with 12 additions and 2 deletions
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4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View File

@@ -1834,7 +1834,7 @@ static int dcn31_populate_dml_pipes_from_context(
return pipe_cnt;
}
static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
{
if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
@@ -1978,7 +1978,7 @@ static void dcn31_calculate_wm_and_dlg_fp(
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
}
static void dcn31_calculate_wm_and_dlg(
void dcn31_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,

10
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
View File

@@ -35,6 +35,16 @@ struct dcn31_resource_pool {
struct resource_pool base;
};
bool dcn31_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate);
void dcn31_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel);
void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
struct resource_pool *dcn31_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);