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arm64: dts: msm8998: efficiency is not valid property

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efficiency comes from downstream. The valid upstream property is
capacity-dmips-mhz but until we can come up with those numbers, remove
this property.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
This commit is contained in:
Amit Kucheria
2019-03-29 15:42:08 +05:30
committed by Andy Gross
parent 503250482c
commit 86f93c93dd
1 changed files with 0 additions and 8 deletions
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8
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@@ -78,7 +78,6 @@ CPU0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@@ -97,7 +96,6 @@ CPU1: cpu@1 {
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
@@ -112,7 +110,6 @@ CPU2: cpu@2 {
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
@@ -127,7 +124,6 @@ CPU3: cpu@3 {
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
@@ -142,7 +138,6 @@ CPU4: cpu@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@@ -161,7 +156,6 @@ CPU5: cpu@101 {
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "arm,arch-cache";
@@ -176,7 +170,6 @@ CPU6: cpu@102 {
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "arm,arch-cache";
@@ -191,7 +184,6 @@ CPU7: cpu@103 {
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "arm,arch-cache";