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Merge tag 'qcom-dt-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt

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Merge "Qualcomm ARM Based Device Tree Updates for v3.15" from Kumar Gala

* Added device tree nodes to enable SMP on msm8660, msm8960, and msm8974
* Added Random Number Generator DT nodes for msm8974 and msm8960 SoCs

* tag 'qcom-dt-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
  ARM: dts: qcom-msm8960-cdp: Add RNG device tree node
  ARM: dts: qcom: Add RNG device tree node
  ARM: dts: qcom: Add nodes necessary for SMP boot

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2014-02-28 16:25:34 +01:00
parent 4289564286 5a229c2a59
commit 86a37e52bb
3 changed files with 159 additions and 0 deletions
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24
arch/arm/boot/dts/qcom-msm8660.dtsi
View File

@@ -9,6 +9,30 @@ / {
compatible = "qcom,msm8660";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,scorpion";
enable-method = "qcom,gcc-msm8660";
cpu@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;

59
arch/arm/boot/dts/qcom-msm8960.dtsi
View File

@@ -9,6 +9,36 @@ / {
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 14 0x304>;
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
cpu@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
cpu@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
interrupts = <0 2 0x4>;
};
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -53,6 +83,28 @@ clock-controller@4000000 {
#reset-cells = <1>;
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
};
saw0: regulator@2089000 {
compatible = "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
compatible = "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
serial@16440000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16440000 0x1000>,
@@ -67,4 +119,11 @@ qcom,ssbi@500000 {
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
rng@1a500000 {
compatible = "qcom,prng";
reg = <0x1a500000 0x200>;
clocks = <&gcc PRNG_CLK>;
clock-names = "core";
};
};

76
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@@ -9,6 +9,49 @@ / {
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 9 0xf04>;
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
cpu@0 {
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
};
cpu@1 {
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
};
cpu@2 {
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
qcom,acc = <&acc2>;
};
cpu@3 {
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
qcom,acc = <&acc3>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
interrupts = <0 2 0x4>;
qcom,saw = <&saw_l2>;
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -91,6 +134,32 @@ frame@f9028000 {
};
};
saw_l2: regulator@f9012000 {
compatible = "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
acc0: clock-controller@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
acc1: clock-controller@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
acc2: clock-controller@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
acc3: clock-controller@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
@@ -117,5 +186,12 @@ serial@f991e000 {
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
};
};