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MIPS: loongson32: Switch to generic core
The generic MIPS core is fully compatible with Loongson-1 SoCs, so migrate Loongson-1 to it. Main changes are: - Merge CPU_LOONGSON1B and CPU_LOONGSON1C into a unified CPU_LOONGSON32, as both are based on the GS232 core. - Consolidate LOONGSON1_LS1B and LOONGSON1_LS1C Kconfig options into MACH_LOONGSON32. - Enable MACH_GENERIC_CORE and remove the legacy custom implementation. - Remove all Loongson-1 platform devices and associated code, which are now obsolete due to Device Tree support. - Misc cleanup. Partially based on earlier work by Jiaxun Yang. Link: https://lore.kernel.org/all/20190411121915.8040-4-jiaxun.yang@flygoat.com/ Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Keguang Zhang
committed by
Thomas Bogendoerfer
Thomas Bogendoerfer
parent
ec7c2a107a
commit
85c4354076
@@ -17017,7 +17017,6 @@ L: linux-mips@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml
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F: arch/mips/boot/dts/loongson/loongson1*
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F: arch/mips/include/asm/mach-loongson32/
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F: arch/mips/loongson32/
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F: drivers/*/*loongson1*
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F: drivers/mtd/nand/raw/loongson1-nand-controller.c
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@@ -480,6 +480,23 @@ config LANTIQ
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config MACH_LOONGSON32
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bool "Loongson 32-bit family of machines"
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select MACH_GENERIC_CORE
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select USE_OF
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select BUILTIN_DTB
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select BOOT_ELF32
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select CEVT_R4K
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select CSRC_R4K
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select COMMON_CLK
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select DMA_NONCOHERENT
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select GENERIC_IRQ_SHOW_LEVEL
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select IRQ_MIPS_CPU
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select LS1X_IRQ
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select SYS_HAS_CPU_LOONGSON32
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select SYS_HAS_EARLY_PRINTK
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select USE_GENERIC_EARLY_PRINTK_8250
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_ZBOOT
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help
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This enables support for the Loongson-1 family of machines.
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@@ -1386,25 +1403,20 @@ config CPU_LOONGSON2F
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have a similar programming interface with FPGA northbridge used in
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Loongson2E.
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config CPU_LOONGSON1B
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bool "Loongson 1B"
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depends on SYS_HAS_CPU_LOONGSON1B
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select CPU_LOONGSON32
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config CPU_LOONGSON32
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bool "Loongson 32-bit CPU"
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depends on SYS_HAS_CPU_LOONGSON32
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select CPU_MIPS32
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select CPU_MIPSR2
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_CPUFREQ
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select LEDS_GPIO_REGISTER
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help
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The Loongson 1B is a 32-bit SoC, which implements the MIPS32
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Release 1 instruction set and part of the MIPS32 Release 2
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instruction set.
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config CPU_LOONGSON1C
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bool "Loongson 1C"
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depends on SYS_HAS_CPU_LOONGSON1C
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select CPU_LOONGSON32
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select LEDS_GPIO_REGISTER
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help
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The Loongson 1C is a 32-bit SoC, which implements the MIPS32
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Release 1 instruction set and part of the MIPS32 Release 2
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instruction set.
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The Loongson GS232 microarchitecture implements the MIPS32 Release 1
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instruction set and part of the MIPS32 Release 2 instruction set.
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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@@ -1839,15 +1851,6 @@ config CPU_LOONGSON2EF
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select CPU_SUPPORTS_HUGEPAGES
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select RTC_MC146818_LIB
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config CPU_LOONGSON32
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bool
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select CPU_MIPS32
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select CPU_MIPSR2
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select CPU_HAS_PREFETCH
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_CPUFREQ
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config CPU_BMIPS32_3300
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select SMP_UP if SMP
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bool
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@@ -1885,10 +1888,7 @@ config SYS_HAS_CPU_LOONGSON2F
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select CPU_SUPPORTS_CPUFREQ
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select CPU_SUPPORTS_ADDRWINCFG if 64BIT
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config SYS_HAS_CPU_LOONGSON1B
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bool
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config SYS_HAS_CPU_LOONGSON1C
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config SYS_HAS_CPU_LOONGSON32
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bool
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config SYS_HAS_CPU_MIPS32_R1
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@@ -2999,8 +2999,8 @@ choice
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prompt "Kernel command line type"
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depends on !CMDLINE_OVERRIDE
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default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
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!MACH_LOONGSON64 && !MIPS_MALTA && \
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!CAVIUM_OCTEON_SOC
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!MACH_LOONGSON64 && !MACH_LOONGSON32 && \
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!MIPS_MALTA && !CAVIUM_OCTEON_SOC
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default MIPS_CMDLINE_FROM_BOOTLOADER
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config MIPS_CMDLINE_FROM_DTB
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@@ -24,8 +24,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
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case CPU_LOONGSON64:
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#endif
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#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
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defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
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#ifdef CONFIG_SYS_HAS_CPU_LOONGSON32
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case CPU_LOONGSON32:
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#endif
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@@ -1,107 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* IRQ mappings for Loongson 1
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*/
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#ifndef __ASM_MACH_LOONGSON32_IRQ_H
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#define __ASM_MACH_LOONGSON32_IRQ_H
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/*
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* CPU core Interrupt Numbers
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*/
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#define MIPS_CPU_IRQ_BASE 0
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#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
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#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
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#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
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#define INT0_IRQ MIPS_CPU_IRQ(2)
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#define INT1_IRQ MIPS_CPU_IRQ(3)
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#define INT2_IRQ MIPS_CPU_IRQ(4)
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#define INT3_IRQ MIPS_CPU_IRQ(5)
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#define INT4_IRQ MIPS_CPU_IRQ(6)
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#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
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#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
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/*
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* INT0~3 Interrupt Numbers
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*/
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#define LS1X_IRQ_BASE MIPS_CPU_IRQS
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#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
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#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
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#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
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#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
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#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
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#endif
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#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
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#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
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#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
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#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
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#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
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#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
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#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
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#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
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#if defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
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#endif
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#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
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#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
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#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
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#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
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#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
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#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
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#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
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#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
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#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
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#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
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#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
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#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
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#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
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#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
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#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
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#endif
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#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
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#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
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#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
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#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
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#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
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#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
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#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
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#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
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#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
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#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
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#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
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#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
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#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
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#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
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#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
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#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
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#endif
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define INTN 4
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define INTN 5
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#endif
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#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
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#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
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#endif /* __ASM_MACH_LOONGSON32_IRQ_H */
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@@ -1,50 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Register mappings for Loongson 1
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*/
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#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
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#define __ASM_MACH_LOONGSON32_LOONGSON1_H
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#if defined(CONFIG_LOONGSON1_LS1B)
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#define DEFAULT_MEMSIZE 64 /* If no memsize provided */
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#elif defined(CONFIG_LOONGSON1_LS1C)
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#define DEFAULT_MEMSIZE 32
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#endif
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/* Loongson 1 Register Bases */
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#define LS1X_MUX_BASE 0x1fd00420
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#define LS1X_INTC_BASE 0x1fd01040
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#define LS1X_GPIO0_BASE 0x1fd010c0
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#define LS1X_GPIO1_BASE 0x1fd010c4
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#define LS1X_DMAC_BASE 0x1fd01160
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#define LS1X_CBUS_BASE 0x1fd011c0
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#define LS1X_EHCI_BASE 0x1fe00000
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#define LS1X_OHCI_BASE 0x1fe08000
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#define LS1X_GMAC0_BASE 0x1fe10000
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#define LS1X_GMAC1_BASE 0x1fe20000
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#define LS1X_UART0_BASE 0x1fe40000
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#define LS1X_UART1_BASE 0x1fe44000
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#define LS1X_UART2_BASE 0x1fe48000
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#define LS1X_UART3_BASE 0x1fe4c000
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#define LS1X_CAN0_BASE 0x1fe50000
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#define LS1X_CAN1_BASE 0x1fe54000
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#define LS1X_I2C0_BASE 0x1fe58000
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#define LS1X_I2C1_BASE 0x1fe68000
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#define LS1X_I2C2_BASE 0x1fe70000
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#define LS1X_PWM0_BASE 0x1fe5c000
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#define LS1X_PWM1_BASE 0x1fe5c010
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#define LS1X_PWM2_BASE 0x1fe5c020
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#define LS1X_PWM3_BASE 0x1fe5c030
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#define LS1X_WDT_BASE 0x1fe5c060
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#define LS1X_RTC_BASE 0x1fe64000
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#define LS1X_AC97_BASE 0x1fe74000
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#define LS1X_NAND_BASE 0x1fe78000
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#define LS1X_CLK_BASE 0x1fe78030
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#include <regs-mux.h>
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#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */
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@@ -1,23 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*/
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#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
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#define __ASM_MACH_LOONGSON32_PLATFORM_H
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#include <linux/platform_device.h>
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extern struct platform_device ls1x_uart_pdev;
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extern struct platform_device ls1x_eth0_pdev;
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extern struct platform_device ls1x_eth1_pdev;
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extern struct platform_device ls1x_ehci_pdev;
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extern struct platform_device ls1x_gpio0_pdev;
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extern struct platform_device ls1x_gpio1_pdev;
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extern struct platform_device ls1x_rtc_pdev;
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extern struct platform_device ls1x_wdt_pdev;
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void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
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void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
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#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
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@@ -1,124 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 MUX Register Definitions.
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*/
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#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
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#define __ASM_MACH_LOONGSON32_REGS_MUX_H
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#define LS1X_MUX_REG(x) \
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((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
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#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
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#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
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#if defined(CONFIG_LOONGSON1_LS1B)
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/* MUX CTRL0 Register Bits */
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#define UART0_USE_PWM23 BIT(28)
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#define UART0_USE_PWM01 BIT(27)
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#define UART1_USE_LCD0_5_6_11 BIT(26)
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#define I2C2_USE_CAN1 BIT(25)
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#define I2C1_USE_CAN0 BIT(24)
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#define NAND3_USE_UART5 BIT(23)
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#define NAND3_USE_UART4 BIT(22)
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#define NAND3_USE_UART1_DAT BIT(21)
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#define NAND3_USE_UART1_CTS BIT(20)
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#define NAND3_USE_PWM23 BIT(19)
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#define NAND3_USE_PWM01 BIT(18)
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#define NAND2_USE_UART5 BIT(17)
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#define NAND2_USE_UART4 BIT(16)
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#define NAND2_USE_UART1_DAT BIT(15)
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#define NAND2_USE_UART1_CTS BIT(14)
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#define NAND2_USE_PWM23 BIT(13)
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#define NAND2_USE_PWM01 BIT(12)
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#define NAND1_USE_UART5 BIT(11)
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#define NAND1_USE_UART4 BIT(10)
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#define NAND1_USE_UART1_DAT BIT(9)
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#define NAND1_USE_UART1_CTS BIT(8)
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#define NAND1_USE_PWM23 BIT(7)
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#define NAND1_USE_PWM01 BIT(6)
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#define GMAC1_USE_UART1 BIT(4)
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#define GMAC1_USE_UART0 BIT(3)
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#define LCD_USE_UART0_DAT BIT(2)
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#define LCD_USE_UART15 BIT(1)
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#define LCD_USE_UART0 BIT(0)
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/* MUX CTRL1 Register Bits */
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#define USB_RESET BIT(31)
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#define SPI1_CS_USE_PWM01 BIT(24)
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#define SPI1_USE_CAN BIT(23)
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#define DISABLE_DDR_CONFSPACE BIT(20)
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#define DDR32TO16EN BIT(16)
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#define GMAC1_SHUT BIT(13)
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#define GMAC0_SHUT BIT(12)
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#define USB_SHUT BIT(11)
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#define UART1_3_USE_CAN1 BIT(5)
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#define UART1_2_USE_CAN0 BIT(4)
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#define GMAC1_USE_TXCLK BIT(3)
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#define GMAC0_USE_TXCLK BIT(2)
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#define GMAC1_USE_PWM23 BIT(1)
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#define GMAC0_USE_PWM01 BIT(0)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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|
||||
/* SHUT_CTRL Register Bits */
|
||||
#define UART_SPLIT GENMASK(31, 30)
|
||||
#define OUTPUT_CLK GENMASK(29, 26)
|
||||
#define ADC_SHUT BIT(25)
|
||||
#define SDIO_SHUT BIT(24)
|
||||
#define DMA2_SHUT BIT(23)
|
||||
#define DMA1_SHUT BIT(22)
|
||||
#define DMA0_SHUT BIT(21)
|
||||
#define SPI1_SHUT BIT(20)
|
||||
#define SPI0_SHUT BIT(19)
|
||||
#define I2C2_SHUT BIT(18)
|
||||
#define I2C1_SHUT BIT(17)
|
||||
#define I2C0_SHUT BIT(16)
|
||||
#define AC97_SHUT BIT(15)
|
||||
#define I2S_SHUT BIT(14)
|
||||
#define UART3_SHUT BIT(13)
|
||||
#define UART2_SHUT BIT(12)
|
||||
#define UART1_SHUT BIT(11)
|
||||
#define UART0_SHUT BIT(10)
|
||||
#define CAN1_SHUT BIT(9)
|
||||
#define CAN0_SHUT BIT(8)
|
||||
#define ECC_SHUT BIT(7)
|
||||
#define GMAC_SHUT BIT(6)
|
||||
#define USBHOST_SHUT BIT(5)
|
||||
#define USBOTG_SHUT BIT(4)
|
||||
#define SDRAM_SHUT BIT(3)
|
||||
#define SRAM_SHUT BIT(2)
|
||||
#define CAM_SHUT BIT(1)
|
||||
#define LCD_SHUT BIT(0)
|
||||
|
||||
#define UART_SPLIT_SHIFT 30
|
||||
#define OUTPUT_CLK_SHIFT 26
|
||||
|
||||
/* MISC_CTRL Register Bits */
|
||||
#define USBHOST_RSTN BIT(31)
|
||||
#define PHY_INTF_SELI GENMASK(30, 28)
|
||||
#define AC97_EN BIT(25)
|
||||
#define SDIO_DMA_EN GENMASK(24, 23)
|
||||
#define ADC_DMA_EN BIT(22)
|
||||
#define SDIO_USE_SPI1 BIT(17)
|
||||
#define SDIO_USE_SPI0 BIT(16)
|
||||
#define SRAM_CTRL GENMASK(15, 0)
|
||||
|
||||
#define PHY_INTF_SELI_SHIFT 28
|
||||
#define SDIO_DMA_EN_SHIFT 23
|
||||
#define SRAM_CTRL_SHIFT 0
|
||||
|
||||
#define LS1X_CBUS_REG(n, x) \
|
||||
((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
|
||||
|
||||
#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
|
||||
#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
|
||||
#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
|
||||
#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
|
||||
#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
|
||||
@@ -1,41 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
if MACH_LOONGSON32
|
||||
|
||||
choice
|
||||
prompt "Machine Type"
|
||||
|
||||
config LOONGSON1_LS1B
|
||||
bool "Loongson LS1B board"
|
||||
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
|
||||
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
|
||||
select SYS_HAS_CPU_LOONGSON1B
|
||||
select DMA_NONCOHERENT
|
||||
select BOOT_ELF32
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select USE_GENERIC_EARLY_PRINTK_8250
|
||||
select COMMON_CLK
|
||||
|
||||
config LOONGSON1_LS1C
|
||||
bool "Loongson LS1C board"
|
||||
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
|
||||
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
|
||||
select SYS_HAS_CPU_LOONGSON1C
|
||||
select DMA_NONCOHERENT
|
||||
select BOOT_ELF32
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select USE_GENERIC_EARLY_PRINTK_8250
|
||||
select COMMON_CLK
|
||||
endchoice
|
||||
|
||||
endif # MACH_LOONGSON32
|
||||
|
||||
config BUILTIN_DTB_NAME
|
||||
string "Source file for built-in DTB"
|
||||
|
||||
@@ -1,18 +1 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Common code for all Loongson 1 based systems
|
||||
#
|
||||
|
||||
obj-$(CONFIG_MACH_LOONGSON32) += common/
|
||||
|
||||
#
|
||||
# Loongson LS1B board
|
||||
#
|
||||
|
||||
obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
|
||||
|
||||
#
|
||||
# Loongson LS1C board
|
||||
#
|
||||
|
||||
obj-$(CONFIG_LOONGSON1_LS1C) += ls1c/
|
||||
|
||||
@@ -1,3 +1,2 @@
|
||||
cflags-$(CONFIG_CPU_LOONGSON32) += -march=mips32r2 -Wa,--trap
|
||||
cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
|
||||
load-$(CONFIG_CPU_LOONGSON32) += 0xffffffff80200000
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Makefile for common code of loongson1 based machines.
|
||||
#
|
||||
|
||||
obj-y += time.o irq.o platform.o prom.o setup.o
|
||||
@@ -1,191 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
|
||||
#include <loongson1.h>
|
||||
#include <irq.h>
|
||||
|
||||
#define LS1X_INTC_REG(n, x) \
|
||||
((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
|
||||
|
||||
#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
|
||||
#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
|
||||
#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
|
||||
#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
|
||||
#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
|
||||
#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
|
||||
|
||||
static void ls1x_irq_ack(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
|
||||
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
|
||||
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
|
||||
| (1 << bit), LS1X_INTC_INTCLR(n));
|
||||
}
|
||||
|
||||
static void ls1x_irq_mask(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
|
||||
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
|
||||
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTIEN(n));
|
||||
}
|
||||
|
||||
static void ls1x_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
|
||||
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
|
||||
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTIEN(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
|
||||
| (1 << bit), LS1X_INTC_INTCLR(n));
|
||||
}
|
||||
|
||||
static void ls1x_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
|
||||
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
|
||||
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
|
||||
| (1 << bit), LS1X_INTC_INTIEN(n));
|
||||
}
|
||||
|
||||
static int ls1x_irq_settype(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
|
||||
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
|
||||
| (1 << bit), LS1X_INTC_INTPOL(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTEDGE(n));
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTPOL(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTEDGE(n));
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
|
||||
| (1 << bit), LS1X_INTC_INTPOL(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
|
||||
| (1 << bit), LS1X_INTC_INTEDGE(n));
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTPOL(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
|
||||
| (1 << bit), LS1X_INTC_INTEDGE(n));
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
|
||||
& ~(1 << bit), LS1X_INTC_INTPOL(n));
|
||||
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
|
||||
| (1 << bit), LS1X_INTC_INTEDGE(n));
|
||||
break;
|
||||
case IRQ_TYPE_NONE:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip ls1x_irq_chip = {
|
||||
.name = "LS1X-INTC",
|
||||
.irq_ack = ls1x_irq_ack,
|
||||
.irq_mask = ls1x_irq_mask,
|
||||
.irq_mask_ack = ls1x_irq_mask_ack,
|
||||
.irq_unmask = ls1x_irq_unmask,
|
||||
.irq_set_type = ls1x_irq_settype,
|
||||
};
|
||||
|
||||
static void ls1x_irq_dispatch(int n)
|
||||
{
|
||||
u32 int_status, irq;
|
||||
|
||||
/* Get pending sources, masked by current enables */
|
||||
int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
|
||||
__raw_readl(LS1X_INTC_INTIEN(n));
|
||||
|
||||
if (int_status) {
|
||||
irq = LS1X_IRQ(n, __ffs(int_status));
|
||||
do_IRQ(irq);
|
||||
}
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending;
|
||||
|
||||
pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(TIMER_IRQ);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
ls1x_irq_dispatch(0); /* INT0 */
|
||||
else if (pending & CAUSEF_IP3)
|
||||
ls1x_irq_dispatch(1); /* INT1 */
|
||||
else if (pending & CAUSEF_IP4)
|
||||
ls1x_irq_dispatch(2); /* INT2 */
|
||||
else if (pending & CAUSEF_IP5)
|
||||
ls1x_irq_dispatch(3); /* INT3 */
|
||||
else if (pending & CAUSEF_IP6)
|
||||
ls1x_irq_dispatch(4); /* INT4 */
|
||||
else
|
||||
spurious_interrupt();
|
||||
|
||||
}
|
||||
|
||||
static void __init ls1x_irq_init(int base)
|
||||
{
|
||||
int n;
|
||||
|
||||
/* Disable interrupts and clear pending,
|
||||
* setup all IRQs as high level triggered
|
||||
*/
|
||||
for (n = 0; n < INTN; n++) {
|
||||
__raw_writel(0x0, LS1X_INTC_INTIEN(n));
|
||||
__raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
|
||||
__raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
|
||||
/* set DMA0, DMA1 and DMA2 to edge trigger */
|
||||
__raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
|
||||
}
|
||||
|
||||
|
||||
for (n = base; n < NR_IRQS; n++) {
|
||||
irq_set_chip_and_handler(n, &ls1x_irq_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
if (request_irq(INT0_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
|
||||
pr_err("Failed to request irq %d (cascade)\n", INT0_IRQ);
|
||||
if (request_irq(INT1_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
|
||||
pr_err("Failed to request irq %d (cascade)\n", INT1_IRQ);
|
||||
if (request_irq(INT2_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
|
||||
pr_err("Failed to request irq %d (cascade)\n", INT2_IRQ);
|
||||
if (request_irq(INT3_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
|
||||
pr_err("Failed to request irq %d (cascade)\n", INT3_IRQ);
|
||||
#if defined(CONFIG_LOONGSON1_LS1C)
|
||||
if (request_irq(INT4_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
|
||||
pr_err("Failed to request irq %d (cascade)\n", INT4_IRQ);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
mips_cpu_irq_init();
|
||||
ls1x_irq_init(LS1X_IRQ_BASE);
|
||||
}
|
||||
@@ -1,285 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/stmmac.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
|
||||
#include <platform.h>
|
||||
#include <loongson1.h>
|
||||
|
||||
/* 8250/16550 compatible UART */
|
||||
#define LS1X_UART(_id) \
|
||||
{ \
|
||||
.mapbase = LS1X_UART ## _id ## _BASE, \
|
||||
.irq = LS1X_UART ## _id ## _IRQ, \
|
||||
.iotype = UPIO_MEM, \
|
||||
.flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
|
||||
.type = PORT_16550A, \
|
||||
}
|
||||
|
||||
static struct plat_serial8250_port ls1x_serial8250_pdata[] = {
|
||||
LS1X_UART(0),
|
||||
LS1X_UART(1),
|
||||
LS1X_UART(2),
|
||||
LS1X_UART(3),
|
||||
{},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_uart_pdev = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = ls1x_serial8250_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
void __init ls1x_serial_set_uartclk(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct plat_serial8250_port *p;
|
||||
|
||||
clk = clk_get(&pdev->dev, pdev->name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("unable to get %s clock, err=%ld",
|
||||
pdev->name, PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
for (p = pdev->dev.platform_data; p->flags != 0; ++p)
|
||||
p->uartclk = clk_get_rate(clk);
|
||||
}
|
||||
|
||||
/* Synopsys Ethernet GMAC */
|
||||
static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
|
||||
.phy_mask = 0,
|
||||
};
|
||||
|
||||
static struct stmmac_dma_cfg ls1x_eth_dma_cfg = {
|
||||
.pbl = 1,
|
||||
};
|
||||
|
||||
int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
|
||||
{
|
||||
struct plat_stmmacenet_data *plat_dat = NULL;
|
||||
u32 val;
|
||||
|
||||
val = __raw_readl(LS1X_MUX_CTRL1);
|
||||
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
plat_dat = dev_get_platdata(&pdev->dev);
|
||||
if (plat_dat->bus_id) {
|
||||
__raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
|
||||
GMAC1_USE_UART0, LS1X_MUX_CTRL0);
|
||||
switch (plat_dat->phy_interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val &= ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
val |= (GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
|
||||
break;
|
||||
default:
|
||||
pr_err("unsupported mii mode %d\n",
|
||||
plat_dat->phy_interface);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
val &= ~GMAC1_SHUT;
|
||||
} else {
|
||||
switch (plat_dat->phy_interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val &= ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
val |= (GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
|
||||
break;
|
||||
default:
|
||||
pr_err("unsupported mii mode %d\n",
|
||||
plat_dat->phy_interface);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
val &= ~GMAC0_SHUT;
|
||||
}
|
||||
__raw_writel(val, LS1X_MUX_CTRL1);
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
plat_dat = dev_get_platdata(&pdev->dev);
|
||||
|
||||
val &= ~PHY_INTF_SELI;
|
||||
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RMII)
|
||||
val |= 0x4 << PHY_INTF_SELI_SHIFT;
|
||||
__raw_writel(val, LS1X_MUX_CTRL1);
|
||||
|
||||
val = __raw_readl(LS1X_MUX_CTRL0);
|
||||
__raw_writel(val & (~GMAC_SHUT), LS1X_MUX_CTRL0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct plat_stmmacenet_data ls1x_eth0_pdata = {
|
||||
.bus_id = 0,
|
||||
.phy_addr = -1,
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
.phy_interface = PHY_INTERFACE_MODE_RMII,
|
||||
#endif
|
||||
.mdio_bus_data = &ls1x_mdio_bus_data,
|
||||
.dma_cfg = &ls1x_eth_dma_cfg,
|
||||
.has_gmac = 1,
|
||||
.tx_coe = 1,
|
||||
.rx_queues_to_use = 1,
|
||||
.tx_queues_to_use = 1,
|
||||
.init = ls1x_eth_mux_init,
|
||||
};
|
||||
|
||||
static struct resource ls1x_eth0_resources[] = {
|
||||
[0] = {
|
||||
.start = LS1X_GMAC0_BASE,
|
||||
.end = LS1X_GMAC0_BASE + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = "macirq",
|
||||
.start = LS1X_GMAC0_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_eth0_pdev = {
|
||||
.name = "stmmaceth",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(ls1x_eth0_resources),
|
||||
.resource = ls1x_eth0_resources,
|
||||
.dev = {
|
||||
.platform_data = &ls1x_eth0_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_LOONGSON1_LS1B
|
||||
static struct plat_stmmacenet_data ls1x_eth1_pdata = {
|
||||
.bus_id = 1,
|
||||
.phy_addr = -1,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.mdio_bus_data = &ls1x_mdio_bus_data,
|
||||
.dma_cfg = &ls1x_eth_dma_cfg,
|
||||
.has_gmac = 1,
|
||||
.tx_coe = 1,
|
||||
.rx_queues_to_use = 1,
|
||||
.tx_queues_to_use = 1,
|
||||
.init = ls1x_eth_mux_init,
|
||||
};
|
||||
|
||||
static struct resource ls1x_eth1_resources[] = {
|
||||
[0] = {
|
||||
.start = LS1X_GMAC1_BASE,
|
||||
.end = LS1X_GMAC1_BASE + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = "macirq",
|
||||
.start = LS1X_GMAC1_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_eth1_pdev = {
|
||||
.name = "stmmaceth",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(ls1x_eth1_resources),
|
||||
.resource = ls1x_eth1_resources,
|
||||
.dev = {
|
||||
.platform_data = &ls1x_eth1_pdata,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_LOONGSON1_LS1B */
|
||||
|
||||
/* GPIO */
|
||||
static struct resource ls1x_gpio0_resources[] = {
|
||||
[0] = {
|
||||
.start = LS1X_GPIO0_BASE,
|
||||
.end = LS1X_GPIO0_BASE + SZ_4 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_gpio0_pdev = {
|
||||
.name = "ls1x-gpio",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(ls1x_gpio0_resources),
|
||||
.resource = ls1x_gpio0_resources,
|
||||
};
|
||||
|
||||
static struct resource ls1x_gpio1_resources[] = {
|
||||
[0] = {
|
||||
.start = LS1X_GPIO1_BASE,
|
||||
.end = LS1X_GPIO1_BASE + SZ_4 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_gpio1_pdev = {
|
||||
.name = "ls1x-gpio",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(ls1x_gpio1_resources),
|
||||
.resource = ls1x_gpio1_resources,
|
||||
};
|
||||
|
||||
/* USB EHCI */
|
||||
static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct resource ls1x_ehci_resources[] = {
|
||||
[0] = {
|
||||
.start = LS1X_EHCI_BASE,
|
||||
.end = LS1X_EHCI_BASE + SZ_32K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = LS1X_EHCI_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct usb_ehci_pdata ls1x_ehci_pdata = {
|
||||
};
|
||||
|
||||
struct platform_device ls1x_ehci_pdev = {
|
||||
.name = "ehci-platform",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(ls1x_ehci_resources),
|
||||
.resource = ls1x_ehci_resources,
|
||||
.dev = {
|
||||
.dma_mask = &ls1x_ehci_dmamask,
|
||||
.platform_data = &ls1x_ehci_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
/* Real Time Clock */
|
||||
struct platform_device ls1x_rtc_pdev = {
|
||||
.name = "ls1x-rtc",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
/* Watchdog */
|
||||
static struct resource ls1x_wdt_resources[] = {
|
||||
{
|
||||
.start = LS1X_WDT_BASE,
|
||||
.end = LS1X_WDT_BASE + SZ_16 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device ls1x_wdt_pdev = {
|
||||
.name = "ls1x-wdt",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(ls1x_wdt_resources),
|
||||
.resource = ls1x_wdt_resources,
|
||||
};
|
||||
@@ -1,42 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*
|
||||
* Modified from arch/mips/pnx833x/common/prom.c.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/fw/fw.h>
|
||||
|
||||
#include <loongson1.h>
|
||||
|
||||
unsigned long memsize;
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
void __iomem *uart_base;
|
||||
|
||||
fw_init_cmdline();
|
||||
|
||||
memsize = fw_getenvl("memsize");
|
||||
if(!memsize)
|
||||
memsize = DEFAULT_MEMSIZE;
|
||||
|
||||
if (strstr(arcs_cmdline, "console=ttyS3"))
|
||||
uart_base = ioremap(LS1X_UART3_BASE, 0x0f);
|
||||
else if (strstr(arcs_cmdline, "console=ttyS2"))
|
||||
uart_base = ioremap(LS1X_UART2_BASE, 0x0f);
|
||||
else if (strstr(arcs_cmdline, "console=ttyS1"))
|
||||
uart_base = ioremap(LS1X_UART1_BASE, 0x0f);
|
||||
else
|
||||
uart_base = ioremap(LS1X_UART0_BASE, 0x0f);
|
||||
setup_8250_early_printk_port((unsigned long)uart_base, 0, 0);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
memblock_add(0x0, (memsize << 20));
|
||||
}
|
||||
@@ -1,26 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
unsigned int processor_id = (¤t_cpu_data)->processor_id;
|
||||
|
||||
switch (processor_id & PRID_REV_MASK) {
|
||||
case PRID_REV_LOONGSON1B:
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
return "LOONGSON LS1B";
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
return "LOONGSON LS1C";
|
||||
#endif
|
||||
default:
|
||||
return "LOONGSON (unknown)";
|
||||
}
|
||||
}
|
||||
@@ -1,23 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct clk *clk = NULL;
|
||||
|
||||
/* initialize LS1X clocks */
|
||||
of_clk_init(NULL);
|
||||
|
||||
/* setup mips r4k timer */
|
||||
clk = clk_get(NULL, "cpu_clk");
|
||||
if (IS_ERR(clk))
|
||||
panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
}
|
||||
@@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Makefile for loongson1B based machines.
|
||||
#
|
||||
|
||||
obj-y += board.o
|
||||
@@ -1,55 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/leds.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <loongson1.h>
|
||||
#include <platform.h>
|
||||
|
||||
static const struct gpio_led ls1x_gpio_leds[] __initconst = {
|
||||
{
|
||||
.name = "LED9",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = 38,
|
||||
.active_low = 1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
}, {
|
||||
.name = "LED6",
|
||||
.default_trigger = "nand-disk",
|
||||
.gpio = 39,
|
||||
.active_low = 1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data ls1x_led_pdata __initconst = {
|
||||
.num_leds = ARRAY_SIZE(ls1x_gpio_leds),
|
||||
.leds = ls1x_gpio_leds,
|
||||
};
|
||||
|
||||
static struct platform_device *ls1b_platform_devices[] __initdata = {
|
||||
&ls1x_uart_pdev,
|
||||
&ls1x_eth0_pdev,
|
||||
&ls1x_eth1_pdev,
|
||||
&ls1x_ehci_pdev,
|
||||
&ls1x_gpio0_pdev,
|
||||
&ls1x_gpio1_pdev,
|
||||
&ls1x_rtc_pdev,
|
||||
&ls1x_wdt_pdev,
|
||||
};
|
||||
|
||||
static int __init ls1b_platform_init(void)
|
||||
{
|
||||
ls1x_serial_set_uartclk(&ls1x_uart_pdev);
|
||||
|
||||
gpio_led_register_device(-1, &ls1x_led_pdata);
|
||||
|
||||
return platform_add_devices(ls1b_platform_devices,
|
||||
ARRAY_SIZE(ls1b_platform_devices));
|
||||
}
|
||||
|
||||
arch_initcall(ls1b_platform_init);
|
||||
@@ -1,6 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Makefile for loongson1C based machines.
|
||||
#
|
||||
|
||||
obj-y += board.o
|
||||
@@ -1,23 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
|
||||
*/
|
||||
|
||||
#include <platform.h>
|
||||
|
||||
static struct platform_device *ls1c_platform_devices[] __initdata = {
|
||||
&ls1x_uart_pdev,
|
||||
&ls1x_eth0_pdev,
|
||||
&ls1x_rtc_pdev,
|
||||
&ls1x_wdt_pdev,
|
||||
};
|
||||
|
||||
static int __init ls1c_platform_init(void)
|
||||
{
|
||||
ls1x_serial_set_uartclk(&ls1x_uart_pdev);
|
||||
|
||||
return platform_add_devices(ls1c_platform_devices,
|
||||
ARRAY_SIZE(ls1c_platform_devices));
|
||||
}
|
||||
|
||||
arch_initcall(ls1c_platform_init);
|
||||
Reference in New Issue
Block a user