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clk: samsung: exynosautov920: add cpucl1/2 clock support
Register compatible and cmu_info data to support clock CPUCL1/2 (CPU Cluster 1 and CPU Cluster 2), these provide clock for CPUCL1/2_SWTICH/CLUSTER. These clocks are required early during boot for the CPUs, so they are declared using CLK_OF_DECLARE instead of being registered through a platform driver. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-3-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Shin Son
committed by
Krzysztof Kozlowski
Krzysztof Kozlowski
parent
22493f2231
commit
84d36f26d0
@@ -19,6 +19,8 @@
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/* NOTE: Must be equal to the last clock ID increased by one */
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#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
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#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
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#define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
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#define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
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#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
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#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
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#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
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@@ -1135,6 +1137,210 @@ static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
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CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
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exynosautov920_cmu_cpucl0_init);
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/* ---- CMU_CPUCL1 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
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#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
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#define PLL_CON0_PLL_CPUCL1 0x0100
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#define PLL_CON1_PLL_CPUCL1 0x0104
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#define PLL_CON3_PLL_CPUCL1 0x010c
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#define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
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#define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
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#define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
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#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
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#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
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#define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
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#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
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#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
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#define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
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static const unsigned long cpucl1_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_CPUCL1,
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PLL_CON0_PLL_CPUCL1,
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PLL_CON1_PLL_CPUCL1,
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PLL_CON3_PLL_CPUCL1,
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PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
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CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
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CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
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CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
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CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
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};
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/* List of parent clocks for Muxes in CMU_CPUCL1 */
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PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
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PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
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PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
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PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
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"mout_cpucl1_switch_user"};
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PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
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"mout_cpucl1_switch_user"};
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static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
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/* CMU_CPUCL1_PURECLKCOMP */
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PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
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PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
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};
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static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
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MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
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PLL_CON0_PLL_CPUCL1, 4, 1),
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MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
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CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
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MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
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CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
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};
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static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
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DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
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DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
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"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
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};
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static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
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.pll_clks = cpucl1_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
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.mux_clks = cpucl1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
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.div_clks = cpucl1_div_clks,
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.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
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.nr_clk_ids = CLKS_NR_CPUCL1,
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.clk_regs = cpucl1_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
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.clk_name = "cpucl1",
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};
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static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
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{
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exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
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}
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/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
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CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
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exynosautov920_cmu_cpucl1_init);
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/* ---- CMU_CPUCL2 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
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#define PLL_LOCKTIME_PLL_CPUCL2 0x0000
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#define PLL_CON0_PLL_CPUCL2 0x0100
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#define PLL_CON1_PLL_CPUCL2 0x0104
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#define PLL_CON3_PLL_CPUCL2 0x010c
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#define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
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#define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
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#define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
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#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
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#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
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#define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
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#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
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#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
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#define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
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static const unsigned long cpucl2_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_CPUCL2,
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PLL_CON0_PLL_CPUCL2,
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PLL_CON1_PLL_CPUCL2,
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PLL_CON3_PLL_CPUCL2,
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PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
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PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
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CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
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CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
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CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
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CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
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CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
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};
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/* List of parent clocks for Muxes in CMU_CPUCL2 */
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PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
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PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
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PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
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PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
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"mout_cpucl2_switch_user"};
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PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
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"mout_cpucl2_switch_user"};
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static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
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/* CMU_CPUCL2_PURECLKCOMP */
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PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
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PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
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};
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static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
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MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
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PLL_CON0_PLL_CPUCL2, 4, 1),
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MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
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PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
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MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
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CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
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MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
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CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
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};
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static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
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DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
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DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
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DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
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"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
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};
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static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
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.pll_clks = cpucl2_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
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.mux_clks = cpucl2_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
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.div_clks = cpucl2_div_clks,
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.nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
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.nr_clk_ids = CLKS_NR_CPUCL2,
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.clk_regs = cpucl2_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
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.clk_name = "cpucl2",
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};
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static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
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{
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exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
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}
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/* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
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CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
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exynosautov920_cmu_cpucl2_init);
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/* ---- CMU_PERIC0 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
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