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arm64: dts: qcom: msm8953: Add CCI nodes

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Add the nodes for the camera I2C bus on the MSM8953 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Link: https://lore.kernel.org/r/20251028-msm8953-cci-v2-5-b5f9f7135326@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Luca Weiss
2025-10-28 17:40:50 +01:00
committed by Bjorn Andersson
parent 589deb6bc2
commit 842c0aa3e0
1 changed files with 57 additions and 0 deletions
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57
arch/arm64/boot/dts/qcom/msm8953.dtsi
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@@ -753,6 +753,20 @@ i2c_6_sleep: i2c-6-sleep-state {
bias-disable;
};
cci0_default: cci0-default-state {
pins = "gpio29", "gpio30";
function = "cci_i2c";
drive-strength = <2>;
bias-disable;
};
cci1_default: cci1-default-state {
pins = "gpio31", "gpio32";
function = "cci_i2c";
drive-strength = <2>;
bias-disable;
};
wcnss_pin_a: wcnss-active-state {
wcss-wlan2-pins {
pins = "gpio76";
@@ -1200,6 +1214,49 @@ mdss_dsi1_phy: phy@1a96400 {
};
};
cci: cci@1b0c000 {
compatible = "qcom,msm8953-cci";
reg = <0x1b0c000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
<&gcc GCC_CAMSS_CCI_AHB_CLK>,
<&gcc GCC_CAMSS_CCI_CLK>,
<&gcc GCC_CAMSS_AHB_CLK>;
clock-names = "camss_top_ahb",
"cci_ahb",
"cci",
"camss_ahb";
assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
<&gcc GCC_CAMSS_CCI_CLK>;
assigned-clock-rates = <80000000>,
<19200000>;
pinctrl-0 = <&cci0_default &cci1_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
gpu: gpu@1c00000 {
compatible = "qcom,adreno-506.0", "qcom,adreno";
reg = <0x01c00000 0x40000>;