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Merge tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Browse Source 
Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Add camera, display and GPU clock drivers for Qualcomm SM4450
 - Add a camera clock driver for Qualcomm SM8150
 - Mark a bunch of struct freq_tbl const to reduce .data usage
 - Add Qualcomm MSM8226 A7PLL and Regera PLL support
 - Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse
   Trion, as they do differ
 - A number of fixes to the Qualcomm SM8550 display clock driver
 - Fold Qualcomm SM8650 display clock driver into SM8550 one
 - Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998
 - Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X
 - Fix sdcc clk frequency tables on Qualcomm SC8180X
 - Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src
 - Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid them
   turning off during suspend
 - Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller
   GDSCs

* tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits)
  clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's
  clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL
  clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks
  clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks
  clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src
  dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details
  dt-bindings: interconnect: Add Qualcomm IPQ5332 support
  clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks
  dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
  clk: qcom: Fix SM_CAMCC_8150 dependencies
  clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
  clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table
  clk: qcom: gcc-sc8180x: Add GPLL9 support
  dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x
  clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x
  clk: qcom: clk-rpmh: Fix overflow in BCM vote
  dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc
  dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc
  dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema
  dt-bindings: clock: Add x1e80100 LPASSCC reset controller
  ...
This commit is contained in:
Stephen Boyd
2024-09-18 09:44:48 -07:00
parent 8400291e28 d628455ab3
commit 82cf3b8afc
54 changed files with 6843 additions and 2380 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@@ -21,6 +21,7 @@ properties:
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,ipq9574-a73pll
- qcom,msm8226-a7pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll
@@ -40,6 +41,9 @@ properties:
operating-points-v2: true
opp-table:
type: object
required:
- compatible
- reg

2
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
View File

@@ -31,6 +31,8 @@ properties:
- description: USB PCIE wrapper pipe clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible

47
Documentation/devicetree/bindings/clock/qcom,qcs404-turingcc.yaml Normal file
View File

@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Turing Clock & Reset Controller on QCS404
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
const: qcom,qcs404-turingcc
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
clock-controller@800000 {
compatible = "qcom,qcs404-turingcc";
reg = <0x00800000 0x30000>;
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};

13
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
View File

@@ -18,9 +18,16 @@ description: |
properties:
compatible:
enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
oneOf:
- enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
- items:
- const: qcom,x1e80100-lpassaudiocc
- const: qcom,sc8280xp-lpassaudiocc
- items:
- const: qcom,x1e80100-lpasscc
- const: qcom,sc8280xp-lpasscc
reg:
maxItems: 1

63
Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml Normal file
View File

@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

71
Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml Normal file
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

77
Documentation/devicetree/bindings/clock/qcom,sm8150-camcc.yaml Normal file
View File

@@ -0,0 +1,77 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM8150
maintainers:
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8150.
See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
properties:
compatible:
const: qcom,sm8150-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock from GCC
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ad00000 {
compatible = "qcom,sm8150-camcc";
reg = <0x0ad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
power-domains = <&rpmhpd SM8150_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

19
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@@ -21,9 +21,6 @@ description: |
include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
@@ -57,7 +54,21 @@ required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
then:
required:
- required-opps
unevaluatedProperties: false

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc

11
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -44,11 +44,20 @@ required:
- compatible
- clocks
- power-domains
- required-opps
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
then:
required:
- required-opps
unevaluatedProperties: false

19
Documentation/devicetree/bindings/clock/qcom,turingcc.txt
View File

@@ -1,19 +0,0 @@
Qualcomm Turing Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible: shall contain "qcom,qcs404-turingcc".
- reg: shall contain base register location and length.
- clocks: ahb clock for the TuringCC
- #clock-cells: from common clock binding, shall contain 1.
- #reset-cells: from common reset binding, shall contain 1.
Example:
turingcc: clock-controller@800000 {
compatible = "qcom,qcs404-turingcc";
reg = <0x00800000 0x30000>;
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
View File

@@ -164,6 +164,7 @@ allOf:
contains:
enum:
- qcom,ipq4019-dwc3
- qcom,ipq5332-dwc3
then:
properties:
clocks:
@@ -267,7 +268,6 @@ allOf:
contains:
enum:
- qcom,ipq5018-dwc3
- qcom,ipq5332-dwc3
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
then:

51
drivers/clk/qcom/Kconfig
View File

@@ -810,6 +810,14 @@ config SDX_GCC_75
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/eMMC, PCIe etc.
config SM_CAMCC_4450
tristate "SM4450 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_4450
help
Support for the camera clock controller on SM4450 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_6350
tristate "SM6350 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -826,6 +834,16 @@ config SM_CAMCC_7150
Support for the camera clock controller on SM7150 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_8150
tristate "SM8150 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8150
help
Support for the camera clock controller on Qualcomm Technologies, Inc
SM8150 devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config SM_CAMCC_8250
tristate "SM8250 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -858,6 +876,16 @@ config SM_CAMCC_8650
Support for the camera clock controller on SM8650 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_4450
tristate "SM4450 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
depends on SM_GCC_4450
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM4450 devices.
Say Y if you want to support display devices and functionality such as
splash screen
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -931,20 +959,10 @@ config SM_DISPCC_8450
config SM_DISPCC_8550
tristate "SM8550 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
depends on SM_GCC_8550
depends on SM_GCC_8550 || SM_GCC_8650
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM8550 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_8650
tristate "SM8650 Display Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8650
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM8650 devices.
SM8550 or SM8650 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
@@ -1054,6 +1072,15 @@ config SM_GCC_8650
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_4450
tristate "SM4450 Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_4450
help
Support for the graphics clock controller on SM4450 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_GPUCC_6115
tristate "SM6115 Graphics Clock Controller"
select SM_GCC_6115

5
drivers/clk/qcom/Makefile
View File

@@ -107,12 +107,15 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
obj-$(CONFIG_SDX_GCC_75) += gcc-sdx75.o
obj-$(CONFIG_SM_CAMCC_4450) += camcc-sm4450.o
obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
obj-$(CONFIG_SM_DISPCC_4450) += dispcc-sm4450.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
@@ -121,7 +124,6 @@ obj-$(CONFIG_SM_DISPCC_7150) += dispcc-sm7150.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o
obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
@@ -134,6 +136,7 @@ obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
obj-$(CONFIG_SM_GPUCC_4450) += gpucc-sm4450.o
obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o

1
drivers/clk/qcom/a53-pll.c
View File

@@ -151,6 +151,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_a53pll_match_table[] = {
{ .compatible = "qcom,msm8226-a7pll" },
{ .compatible = "qcom,msm8916-a53pll" },
{ .compatible = "qcom,msm8939-a53pll" },
{ }

1688
drivers/clk/qcom/camcc-sm4450.c Normal file
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File diff suppressed because it is too large Load Diff

2159
drivers/clk/qcom/camcc-sm8150.c Normal file
View File

File diff suppressed because it is too large Load Diff

86
drivers/clk/qcom/clk-alpha-pll.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@@ -1712,7 +1712,7 @@ static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
if (ret < 0)
return ret;
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
/* Latch the PLL input */
@@ -1831,6 +1831,58 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
/**
* clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
*
* @pll: clk alpha pll
* @regmap: register map
* @config: configuration to apply for pll
*/
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
/*
* If the bootloader left the PLL enabled it's likely that there are
* RCGs that will lock up if we disable the PLL below.
*/
if (trion_pll_is_enabled(pll, regmap)) {
pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
return;
}
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
config->test_ctl_hi1_val);
/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
/* Set operation mode to OFF */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
/* Place the PLL in STANDBY mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -2657,3 +2709,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
.set_rate = clk_alpha_pll_stromer_plus_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
/* Set operation mode to STANDBY */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
const struct clk_ops clk_alpha_pll_regera_ops = {
.enable = clk_zonda_pll_enable,
.disable = clk_zonda_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);

7
drivers/clk/qcom/clk-alpha-pll.h
View File

@@ -23,6 +23,7 @@ enum {
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
@@ -193,6 +194,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
extern const struct clk_ops clk_alpha_pll_regera_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -208,6 +211,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -216,5 +221,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
const struct alpha_pll_config *config);
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
#endif

2
drivers/clk/qcom/clk-rpmh.c
View File

@@ -263,6 +263,8 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
cmd_state = 0;
}
cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK);
if (c->last_sent_aggr_state != cmd_state) {
cmd.addr = c->res_addr;
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);

770
drivers/clk/qcom/dispcc-sm4450.c Normal file
View File

@@ -0,0 +1,770 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_AHB_CLK,
DT_SLEEP_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
};
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DISP_CC_PLL1_OUT_EVEN,
P_DISP_CC_PLL1_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_SLEEP_CLK,
};
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
/* 600.0 MHz Configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll disp_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
};
static const struct clk_parent_data disp_cc_parent_data_2_ao[] = {
{ .index = DT_BI_TCXO_AO },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x82a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x80f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x8114,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(506000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x80b0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x8098,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x80c8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x80e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0xe058,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_xo_clk_src = {
.cmd_rcgr = 0xe03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_xo_clk_src",
.parent_data = disp_cc_parent_data_2_ao,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x8110,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb1_clk = {
.halt_reg = 0xa020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x8094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x8024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x8028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x802c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp1_clk = {
.halt_reg = 0xa004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x8008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
.halt_reg = 0xa014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x8018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0xc004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x8004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot1_clk = {
.halt_reg = 0xa00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rot1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x8010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0xc00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0xc008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync1_clk = {
.halt_reg = 0xa01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x8020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc disp_cc_mdss_core_gdsc = {
.gdscr = 0x9000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp_cc_mdss_core_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc disp_cc_mdss_core_int2_gdsc = {
.gdscr = 0xb000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp_cc_mdss_core_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm4450_clocks[] = {
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
};
static struct gdsc *disp_cc_sm4450_gdscs[] = {
[DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
[DISP_CC_MDSS_CORE_INT2_GDSC] = &disp_cc_mdss_core_int2_gdsc,
};
static const struct qcom_reset_map disp_cc_sm4450_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
};
static const struct regmap_config disp_cc_sm4450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x11008,
.fast_io = true,
};
static struct qcom_cc_desc disp_cc_sm4450_desc = {
.config = &disp_cc_sm4450_regmap_config,
.clks = disp_cc_sm4450_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm4450_clocks),
.resets = disp_cc_sm4450_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm4450_resets),
.gdscs = disp_cc_sm4450_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm4450_gdscs),
};
static const struct of_device_id disp_cc_sm4450_match_table[] = {
{ .compatible = "qcom,sm4450-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm4450_match_table);
static int disp_cc_sm4450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sm4450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll0_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0xe070); /* DISP_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm4450_desc, regmap);
}
static struct platform_driver disp_cc_sm4450_driver = {
.probe = disp_cc_sm4450_probe,
.driver = {
.name = "dispcc-sm4450",
.of_match_table = disp_cc_sm4450_match_table,
},
};
module_platform_driver(disp_cc_sm4450_driver);
MODULE_DESCRIPTION("QTI DISPCC SM4450 Driver");
MODULE_LICENSE("GPL");

12
drivers/clk/qcom/dispcc-sm8250.c
View File

@@ -849,6 +849,7 @@ static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -884,6 +885,7 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1009,6 +1011,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1357,8 +1360,13 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
} else {
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
}
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x10, 0x10);

198
drivers/clk/qcom/dispcc-sm8550.c
View File

@@ -71,7 +71,7 @@ enum {
P_SLEEP_CLK,
};
static const struct pll_vco lucid_ole_vco[] = {
static struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2000000000, 0 },
};
@@ -95,7 +95,7 @@ static struct clk_alpha_pll disp_cc_pll0 = {
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
@@ -126,7 +126,7 @@ static struct clk_alpha_pll disp_cc_pll1 = {
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
@@ -196,7 +196,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
@@ -213,7 +213,7 @@ static const struct clk_parent_data disp_cc_parent_data_4[] = {
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 4 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
@@ -286,7 +286,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
@@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@@ -321,7 +321,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@@ -336,7 +336,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@@ -350,7 +350,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
@@ -365,7 +365,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
@@ -380,7 +380,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
@@ -395,12 +395,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
.ops = &clk_rcg2_ops,
},
};
@@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
@@ -424,7 +424,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@@ -439,7 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@@ -454,7 +454,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@@ -468,7 +468,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
@@ -483,7 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@@ -498,7 +498,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@@ -513,7 +513,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
@@ -542,7 +542,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
@@ -557,12 +557,12 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@@ -572,12 +572,12 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@@ -594,13 +594,25 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x80d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_8,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_8,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
@@ -615,7 +627,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@@ -630,7 +642,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
@@ -645,7 +657,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
@@ -665,7 +677,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_9,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_9,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
@@ -680,7 +692,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = {
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_xo_clk_src",
.parent_data = disp_cc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
@@ -693,7 +705,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x8120,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
@@ -707,7 +719,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x813c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
@@ -721,7 +733,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
.reg = 0x8188,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
@@ -736,7 +748,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
.reg = 0x821c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
@@ -751,7 +763,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
.reg = 0x8250,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
@@ -766,7 +778,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
.reg = 0x82cc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
@@ -783,7 +795,7 @@ static struct clk_branch disp_cc_mdss_accu_clk = {
.clkr = {
.enable_reg = 0xe058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_accu_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_xo_clk_src.clkr.hw,
@@ -801,7 +813,7 @@ static struct clk_branch disp_cc_mdss_ahb1_clk = {
.clkr = {
.enable_reg = 0xa020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@@ -819,7 +831,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = {
.clkr = {
.enable_reg = 0x80a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@@ -837,7 +849,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
@@ -855,7 +867,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
@@ -873,7 +885,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = {
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
@@ -891,7 +903,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.clkr = {
.enable_reg = 0x8034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
@@ -909,7 +921,7 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
.clkr = {
.enable_reg = 0x8058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
@@ -927,7 +939,7 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
.clkr = {
.enable_reg = 0x804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
@@ -945,7 +957,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
.clkr = {
.enable_reg = 0x8040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
@@ -963,7 +975,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
.clkr = {
.enable_reg = 0x8048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
@@ -981,7 +993,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
.clkr = {
.enable_reg = 0x8050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
@@ -999,7 +1011,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
.clkr = {
.enable_reg = 0x8054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
@@ -1017,7 +1029,7 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
.clkr = {
.enable_reg = 0x8044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
@@ -1035,7 +1047,7 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
.clkr = {
.enable_reg = 0x8074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
@@ -1053,7 +1065,7 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
.clkr = {
.enable_reg = 0x8070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
@@ -1071,7 +1083,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
@@ -1089,7 +1101,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
.clkr = {
.enable_reg = 0x806c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
@@ -1107,7 +1119,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
.clkr = {
.enable_reg = 0x805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
@@ -1125,7 +1137,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
.clkr = {
.enable_reg = 0x8060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
@@ -1143,7 +1155,7 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
.clkr = {
.enable_reg = 0x8068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
@@ -1161,7 +1173,7 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
.clkr = {
.enable_reg = 0x808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
@@ -1179,7 +1191,7 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
.clkr = {
.enable_reg = 0x8088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
@@ -1197,7 +1209,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
.clkr = {
.enable_reg = 0x8080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
@@ -1215,7 +1227,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
.clkr = {
.enable_reg = 0x8084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
@@ -1233,7 +1245,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
.clkr = {
.enable_reg = 0x8078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
@@ -1251,7 +1263,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
.clkr = {
.enable_reg = 0x807c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
@@ -1269,7 +1281,7 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
.clkr = {
.enable_reg = 0x809c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
@@ -1287,7 +1299,7 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
.clkr = {
.enable_reg = 0x80a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
@@ -1305,7 +1317,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
.clkr = {
.enable_reg = 0x8094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
@@ -1323,7 +1335,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
.clkr = {
.enable_reg = 0x8098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
@@ -1341,7 +1353,7 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
@@ -1359,7 +1371,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = {
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc0_clk_src.clkr.hw,
@@ -1377,7 +1389,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = {
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc1_clk_src.clkr.hw,
@@ -1395,7 +1407,7 @@ static struct clk_branch disp_cc_mdss_mdp1_clk = {
.clkr = {
.enable_reg = 0xa004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@@ -1413,7 +1425,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = {
.clkr = {
.enable_reg = 0x800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@@ -1431,7 +1443,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
.clkr = {
.enable_reg = 0xa010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@@ -1449,7 +1461,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.clkr = {
.enable_reg = 0x8018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
@@ -1467,7 +1479,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@@ -1485,7 +1497,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = {
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
@@ -1503,7 +1515,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = {
.clkr = {
.enable_reg = 0x8008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
@@ -1521,7 +1533,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.clkr = {
.enable_reg = 0xc00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
@@ -1539,7 +1551,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
@@ -1557,7 +1569,7 @@ static struct clk_branch disp_cc_mdss_vsync1_clk = {
.clkr = {
.enable_reg = 0xa01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
@@ -1575,7 +1587,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
.clkr = {
.enable_reg = 0x8024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
@@ -1593,7 +1605,7 @@ static struct clk_branch disp_cc_sleep_clk = {
.clkr = {
.enable_reg = 0xe074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.hw.init = &(const struct clk_init_data) {
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_sleep_clk_src.clkr.hw,
@@ -1611,7 +1623,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc mdss_int2_gdsc = {
@@ -1620,7 +1632,7 @@ static struct gdsc mdss_int2_gdsc = {
.name = "mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8550_clocks[] = {
@@ -1739,6 +1751,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = {
static const struct of_device_id disp_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-dispcc" },
{ .compatible = "qcom,sm8650-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
@@ -1762,6 +1775,13 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
goto err_put_rpm;
}
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) {
lucid_ole_vco[0].max_freq = 2100000000;
disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650;
disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw;
}
clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
@@ -1795,5 +1815,5 @@ static struct platform_driver disp_cc_sm8550_driver = {
module_platform_driver(disp_cc_sm8550_driver);
MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver");
MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650 Driver");
MODULE_LICENSE("GPL");

1796
drivers/clk/qcom/dispcc-sm8650.c
View File

File diff suppressed because it is too large Load Diff

36
drivers/clk/qcom/gcc-ipq5332.c
View File

@@ -4,12 +4,14 @@
*/
#include <linux/clk-provider.h>
#include <linux/interconnect-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq5332.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = {
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
/*
* There are no consumers for this GPLL in kernel yet,
* (will be added soon), so the clock framework
* disables this source. But some of the clocks
* initialized by boot loaders uses this source. So we
* need to keep this clock ON. Add the
* CLK_IGNORE_UNUSED flag so the clock will not be
* disabled. Once the consumer in kernel is added, we
* can get rid of this flag.
*/
.flags = CLK_IGNORE_UNUSED,
},
},
};
@@ -3388,6 +3379,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
[GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
@@ -3628,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = {
[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
};
#define IPQ_APPS_ID 5332 /* some unique value */
static struct qcom_icc_hws_data icc_ipq5332_hws[] = {
{ MASTER_SNOC_PCIE3_1_M, SLAVE_SNOC_PCIE3_1_M, GCC_SNOC_PCIE3_1LANE_M_CLK },
{ MASTER_ANOC_PCIE3_1_S, SLAVE_ANOC_PCIE3_1_S, GCC_SNOC_PCIE3_1LANE_S_CLK },
{ MASTER_SNOC_PCIE3_2_M, SLAVE_SNOC_PCIE3_2_M, GCC_SNOC_PCIE3_2LANE_M_CLK },
{ MASTER_ANOC_PCIE3_2_S, SLAVE_ANOC_PCIE3_2_S, GCC_SNOC_PCIE3_2LANE_S_CLK },
{ MASTER_SNOC_USB, SLAVE_SNOC_USB, GCC_SNOC_USB_CLK },
{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
};
static const struct regmap_config gcc_ipq5332_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -3656,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
.clk_hws = gcc_ipq5332_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
.icc_hws = icc_ipq5332_hws,
.num_icc_hws = ARRAY_SIZE(icc_ipq5332_hws),
.icc_first_node_id = IPQ_APPS_ID,
};
static int gcc_ipq5332_probe(struct platform_device *pdev)
@@ -3674,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = {
.driver = {
.name = "gcc-ipq5332",
.of_match_table = gcc_ipq5332_match_table,
.sync_state = icc_sync_state,
},
};

2
drivers/clk/qcom/gcc-ipq6018.c
View File

@@ -2684,7 +2684,7 @@ static struct clk_rcg2 lpass_q6_axim_clk_src = {
},
};
static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
static const struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }

4
drivers/clk/qcom/gcc-ipq806x.c
View File

@@ -390,7 +390,7 @@ static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
@@ -714,7 +714,7 @@ static struct clk_branch gsbi7_uart_clk = {
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },

4
drivers/clk/qcom/gcc-ipq8074.c
View File

@@ -1947,7 +1947,7 @@ static struct clk_regmap_div nss_port6_tx_div_clk_src = {
},
};
static struct freq_tbl ftbl_crypto_clk_src[] = {
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
@@ -1968,7 +1968,7 @@ static struct clk_rcg2 crypto_clk_src = {
},
};
static struct freq_tbl ftbl_gp_clk_src[] = {
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

4
drivers/clk/qcom/gcc-mdm9615.c
View File

@@ -164,7 +164,7 @@ static const struct clk_parent_data gcc_cxo_pll14[] = {
{ .hw = &pll14_vote.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
@@ -437,7 +437,7 @@ static struct clk_branch gsbi5_uart_clk = {
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 960000, P_CXO, 4, 1, 5 },
{ 4800000, P_CXO, 4, 0, 1 },
{ 9600000, P_CXO, 2, 0, 1 },

4
drivers/clk/qcom/gcc-msm8660.c
View File

@@ -82,7 +82,7 @@ static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
{ .fw_name = "cxo", .name = "cxo_board" },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
@@ -712,7 +712,7 @@ static struct clk_branch gsbi12_uart_clk = {
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },

6
drivers/clk/qcom/gcc-msm8960.c
View File

@@ -328,7 +328,7 @@ static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
{ .hw = &pll3.clkr.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
static const struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
@@ -958,7 +958,7 @@ static struct clk_branch gsbi12_uart_clk = {
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
static const struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },
@@ -2940,7 +2940,7 @@ static struct clk_branch adm0_pbus_clk = {
},
};
static struct freq_tbl clk_tbl_ce3[] = {
static const struct freq_tbl clk_tbl_ce3[] = {
{ 48000000, P_PLL8, 8 },
{ 100000000, P_PLL3, 12 },
{ 120000000, P_PLL3, 10 },

54
drivers/clk/qcom/gcc-msm8994.c
View File

@@ -112,7 +112,7 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .hw = &gpll4.clkr.hw },
};
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
@@ -136,7 +136,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
},
};
static struct freq_tbl ftbl_usb30_master_clk_src[] = {
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(125000000, P_GPLL0, 1, 5, 24),
{ }
@@ -156,7 +156,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
},
};
static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
@@ -175,7 +175,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -188,7 +188,7 @@ static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
{ }
};
static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -226,7 +226,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -266,7 +266,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -333,7 +333,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -373,7 +373,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -400,7 +400,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
@@ -516,7 +516,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -570,7 +570,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -678,7 +678,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
},
};
static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
static const struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -789,7 +789,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
},
};
static struct freq_tbl ftbl_gp1_clk_src[] = {
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -810,7 +810,7 @@ static struct clk_rcg2 gp1_clk_src = {
},
};
static struct freq_tbl ftbl_gp2_clk_src[] = {
static const struct freq_tbl ftbl_gp2_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -831,7 +831,7 @@ static struct clk_rcg2 gp2_clk_src = {
},
};
static struct freq_tbl ftbl_gp3_clk_src[] = {
static const struct freq_tbl ftbl_gp3_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -852,7 +852,7 @@ static struct clk_rcg2 gp3_clk_src = {
},
};
static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
F(1011000, P_XO, 1, 1, 19),
{ }
};
@@ -872,7 +872,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
},
};
static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
static const struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
F(125000000, P_XO, 1, 0, 0),
{ }
};
@@ -891,7 +891,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
},
};
static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
static const struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
F(1011000, P_XO, 1, 1, 19),
{ }
};
@@ -925,7 +925,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
},
};
static struct freq_tbl ftbl_pdm2_clk_src[] = {
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
@@ -943,7 +943,7 @@ static struct clk_rcg2 pdm2_clk_src = {
},
};
static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
@@ -955,7 +955,7 @@ static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
{ }
};
static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
static const struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
@@ -981,7 +981,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
},
};
static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
static const struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
@@ -1034,7 +1034,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
},
};
static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
F(105500, P_XO, 1, 1, 182),
{ }
};
@@ -1054,7 +1054,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
},
};
static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
{ }
@@ -1073,7 +1073,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
},
};
static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
{ }
};
@@ -1092,7 +1092,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
},
};
static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};

2
drivers/clk/qcom/gcc-msm8996.c
View File

@@ -359,7 +359,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
},
};
static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),

64
drivers/clk/qcom/gcc-msm8998.c
View File

@@ -2242,7 +2242,7 @@ static struct clk_branch gcc_hmss_trig_clk = {
},
};
static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
@@ -2922,6 +2922,43 @@ static struct clk_branch ssc_cnoc_ahbs_clk = {
},
};
static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
.halt_reg = 0x7D010,
.clkr = {
.enable_reg = 0x7D010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "hlos1_vote_lpass_core_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
.halt_reg = 0x7D014,
.clkr = {
.enable_reg = 0x7D014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "hlos1_vote_lpass_adsp_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x8A040,
.clkr = {
.enable_reg = 0x8A040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_mss_q6_bimc_axi_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
@@ -2953,6 +2990,26 @@ static struct gdsc usb_30_gdsc = {
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_lpass_adsp = {
.gdscr = 0x7d034,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "lpass_adsp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_lpass_core = {
.gdscr = 0x7d038,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "lpass_core_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = ALWAYS_ON,
};
static struct clk_regmap *gcc_msm8998_clocks[] = {
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
@@ -3133,12 +3190,17 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
[HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &hlos1_vote_lpass_core_smmu_clk.clkr,
[HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
};
static struct gdsc *gcc_msm8998_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[UFS_GDSC] = &ufs_gdsc,
[USB_30_GDSC] = &usb_30_gdsc,
[LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp,
[LPASS_CORE_GDSC] = &hlos1_vote_lpass_core,
};
static const struct qcom_reset_map gcc_msm8998_resets[] = {

442
drivers/clk/qcom/gcc-sc8180x.c
View File

@@ -142,6 +142,23 @@ static struct clk_alpha_pll gpll7 = {
},
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gpll9",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_trion_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
@@ -241,7 +258,7 @@ static const struct parent_map gcc_parent_map_7[] = {
static const struct clk_parent_data gcc_parents_7[] = {
{ .fw_name = "bi_tcxo", },
{ .hw = &gpll0.clkr.hw },
{ .name = "gppl9" },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
@@ -260,28 +277,6 @@ static const struct clk_parent_data gcc_parents_8[] = {
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
@@ -609,19 +604,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -630,13 +635,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -645,13 +652,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -660,13 +669,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -675,13 +686,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -690,13 +703,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -705,13 +720,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -720,13 +737,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -735,13 +754,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -750,13 +771,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -765,13 +788,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -780,13 +805,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -795,13 +822,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -810,13 +839,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -825,13 +856,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -840,28 +873,33 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -870,13 +908,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -885,13 +925,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -900,13 +942,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -916,7 +952,7 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
@@ -939,9 +975,8 @@ static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
@@ -1599,25 +1634,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
},
};
/* For CPUSS functionality the AHB clock needs to be left enabled */
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
@@ -3150,25 +3166,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
},
};
/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4819c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_cpuss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
@@ -4284,8 +4281,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
@@ -4422,7 +4417,6 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
@@ -4511,6 +4505,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
[GPLL1] = &gpll1.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL9] = &gpll9.clkr,
};
static const struct qcom_reset_map gcc_sc8180x_resets[] = {
@@ -4546,6 +4541,10 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x50024 },
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x50028 },
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5002c },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50030 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
@@ -4561,6 +4560,29 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
};
static struct gdsc *gcc_sc8180x_gdscs[] = {
[EMAC_GDSC] = &emac_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
@@ -4602,6 +4624,7 @@ MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
static int gcc_sc8180x_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
if (IS_ERR(regmap))
@@ -4623,6 +4646,11 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);
}

6
drivers/clk/qcom/gcc-sm8250.c
View File

@@ -3226,7 +3226,7 @@ static struct gdsc pcie_0_gdsc = {
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc pcie_1_gdsc = {
@@ -3234,7 +3234,7 @@ static struct gdsc pcie_1_gdsc = {
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc pcie_2_gdsc = {
@@ -3242,7 +3242,7 @@ static struct gdsc pcie_2_gdsc = {
.pd = {
.name = "pcie_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_card_gdsc = {

4
drivers/clk/qcom/gcc-sm8450.c
View File

@@ -2974,7 +2974,7 @@ static struct gdsc pcie_0_gdsc = {
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc pcie_1_gdsc = {
@@ -2982,7 +2982,7 @@ static struct gdsc pcie_1_gdsc = {
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_phy_gdsc = {

805
drivers/clk/qcom/gpucc-sm4450.c Normal file
View File

@@ -0,0 +1,805 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm4450-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_EVEN,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL0_OUT_ODD,
P_GPU_CC_PLL1_OUT_EVEN,
P_GPU_CC_PLL1_OUT_MAIN,
P_GPU_CC_PLL1_OUT_ODD,
};
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
/* 680.0 MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x23,
.alpha = 0x6aaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 500.0 MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(340000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(605000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(765000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(850000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(955000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(1010000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x9070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_4,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_4,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x9430,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x919c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x919c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
.halt_reg = 0x91a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x91a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gfx3d_slv_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x9130,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_cxo_clk = {
.halt_reg = 0x90b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_ff_clk = {
.halt_reg = 0x90c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x90a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
.halt_reg = 0x90c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x90bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x90b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cc_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.clk_dis_wait_val = 8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_cc_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.resets = (unsigned int []){ GPU_CC_GX_BCR,
GPU_CC_ACD_BCR,
GPU_CC_GX_ACD_IROOT_BCR },
.reset_count = 3,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm4450_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static struct gdsc *gpu_cc_sm4450_gdscs[] = {
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sm4450_resets[] = {
[GPU_CC_CB_BCR] = { 0x93a0 },
[GPU_CC_CX_BCR] = { 0x9104 },
[GPU_CC_GX_BCR] = { 0x9058 },
[GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPU_CC_ACD_BCR] = { 0x9358 },
[GPU_CC_FF_BCR] = { 0x9470 },
[GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPU_CC_GMU_BCR] = { 0x9314 },
[GPU_CC_RBCPR_BCR] = { 0x91e0 },
[GPU_CC_XO_BCR] = { 0x9000 },
[GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
};
static const struct regmap_config gpu_cc_sm4450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x95c0,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm4450_desc = {
.config = &gpu_cc_sm4450_regmap_config,
.clks = gpu_cc_sm4450_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm4450_clocks),
.resets = gpu_cc_sm4450_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm4450_resets),
.gdscs = gpu_cc_sm4450_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm4450_gdscs),
};
static const struct of_device_id gpu_cc_sm4450_match_table[] = {
{ .compatible = "qcom,sm4450-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm4450_match_table);
static int gpu_cc_sm4450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */
qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */
qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */
return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm4450_desc, regmap);
}
static struct platform_driver gpu_cc_sm4450_driver = {
.probe = gpu_cc_sm4450_probe,
.driver = {
.name = "gpucc-sm4450",
.of_match_table = gpu_cc_sm4450_match_table,
},
};
module_platform_driver(gpu_cc_sm4450_driver);
MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver");
MODULE_LICENSE("GPL");

8
drivers/clk/qcom/lcc-ipq806x.c
View File

@@ -70,7 +70,7 @@ static const struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_mi2s[] = {
static const struct freq_tbl clk_tbl_aif_mi2s[] = {
{ 1024000, P_PLL4, 4, 1, 96 },
{ 1411200, P_PLL4, 4, 2, 139 },
{ 1536000, P_PLL4, 4, 1, 64 },
@@ -214,7 +214,7 @@ static struct clk_regmap_mux mi2s_bit_clk = {
},
};
static struct freq_tbl clk_tbl_pcm[] = {
static const struct freq_tbl clk_tbl_pcm[] = {
{ 64000, P_PLL4, 4, 1, 1536 },
{ 128000, P_PLL4, 4, 1, 768 },
{ 256000, P_PLL4, 4, 1, 384 },
@@ -296,7 +296,7 @@ static struct clk_regmap_mux pcm_clk = {
},
};
static struct freq_tbl clk_tbl_aif_osr[] = {
static const struct freq_tbl clk_tbl_aif_osr[] = {
{ 2822400, P_PLL4, 1, 147, 20480 },
{ 4096000, P_PLL4, 1, 1, 96 },
{ 5644800, P_PLL4, 1, 147, 10240 },
@@ -360,7 +360,7 @@ static struct clk_branch spdif_clk = {
},
};
static struct freq_tbl clk_tbl_ahbix[] = {
static const struct freq_tbl clk_tbl_ahbix[] = {
{ 131072000, P_PLL4, 1, 1, 3 },
{ },
};

8
drivers/clk/qcom/lcc-msm8960.c
View File

@@ -57,7 +57,7 @@ static struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_osr_492[] = {
static const struct freq_tbl clk_tbl_aif_osr_492[] = {
{ 512000, P_PLL4, 4, 1, 240 },
{ 768000, P_PLL4, 4, 1, 160 },
{ 1024000, P_PLL4, 4, 1, 120 },
@@ -73,7 +73,7 @@ static struct freq_tbl clk_tbl_aif_osr_492[] = {
{ }
};
static struct freq_tbl clk_tbl_aif_osr_393[] = {
static const struct freq_tbl clk_tbl_aif_osr_393[] = {
{ 512000, P_PLL4, 4, 1, 192 },
{ 768000, P_PLL4, 4, 1, 128 },
{ 1024000, P_PLL4, 4, 1, 96 },
@@ -218,7 +218,7 @@ CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
static struct freq_tbl clk_tbl_pcm_492[] = {
static const struct freq_tbl clk_tbl_pcm_492[] = {
{ 256000, P_PLL4, 4, 1, 480 },
{ 512000, P_PLL4, 4, 1, 240 },
{ 768000, P_PLL4, 4, 1, 160 },
@@ -235,7 +235,7 @@ static struct freq_tbl clk_tbl_pcm_492[] = {
{ }
};
static struct freq_tbl clk_tbl_pcm_393[] = {
static const struct freq_tbl clk_tbl_pcm_393[] = {
{ 256000, P_PLL4, 4, 1, 384 },
{ 512000, P_PLL4, 4, 1, 192 },
{ 768000, P_PLL4, 4, 1, 128 },

50
drivers/clk/qcom/mmcc-apq8084.c
View File

@@ -338,7 +338,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
},
};
static struct freq_tbl ftbl_mmss_axi_clk[] = {
static const struct freq_tbl ftbl_mmss_axi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
@@ -364,7 +364,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
},
};
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
@@ -389,7 +389,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
},
};
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -447,7 +447,7 @@ static struct clk_rcg2 csi3_clk_src = {
},
};
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
@@ -490,7 +490,7 @@ static struct clk_rcg2 vfe1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@@ -530,7 +530,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
},
};
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -607,7 +607,7 @@ static struct clk_rcg2 pclk1_clk_src = {
},
};
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
@@ -631,7 +631,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
},
};
static struct freq_tbl ftbl_avsync_vp_clk[] = {
static const struct freq_tbl ftbl_avsync_vp_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
@@ -650,7 +650,7 @@ static struct clk_rcg2 vp_clk_src = {
},
};
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -669,7 +669,7 @@ static struct clk_rcg2 cci_clk_src = {
},
};
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
@@ -707,7 +707,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
},
};
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
@@ -777,7 +777,7 @@ static struct clk_rcg2 mclk3_clk_src = {
},
};
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -822,7 +822,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
},
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
@@ -871,7 +871,7 @@ static struct clk_rcg2 byte1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -889,7 +889,7 @@ static struct clk_rcg2 edpaux_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
F(135000000, P_EDPLINK, 2, 0, 0),
F(270000000, P_EDPLINK, 11, 0, 0),
{ }
@@ -909,7 +909,7 @@ static struct clk_rcg2 edplink_clk_src = {
},
};
static struct freq_tbl edp_pixel_freq_tbl[] = {
static const struct freq_tbl edp_pixel_freq_tbl[] = {
{ .src = P_EDPVCO },
{ }
};
@@ -928,7 +928,7 @@ static struct clk_rcg2 edppixel_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -959,7 +959,7 @@ static struct clk_rcg2 esc1_clk_src = {
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
static const struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
@@ -978,7 +978,7 @@ static struct clk_rcg2 extpclk_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -996,7 +996,7 @@ static struct clk_rcg2 hdmi_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -1014,7 +1014,7 @@ static struct clk_rcg2 vsync_clk_src = {
},
};
static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
static const struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
@@ -1032,7 +1032,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
},
};
static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
static const struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -1050,7 +1050,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
},
};
static struct freq_tbl ftbl_vpu_maple_clk[] = {
static const struct freq_tbl ftbl_vpu_maple_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
@@ -1073,7 +1073,7 @@ static struct clk_rcg2 maple_clk_src = {
},
};
static struct freq_tbl ftbl_vpu_vdp_clk[] = {
static const struct freq_tbl ftbl_vpu_vdp_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
@@ -1095,7 +1095,7 @@ static struct clk_rcg2 vdp_clk_src = {
},
};
static struct freq_tbl ftbl_vpu_bus_clk[] = {
static const struct freq_tbl ftbl_vpu_bus_clk[] = {
F(40000000, P_GPLL0, 15, 0, 0),
F(80000000, P_MMPLL0, 10, 0, 0),
{ }

30
drivers/clk/qcom/mmcc-msm8960.c
View File

@@ -155,7 +155,7 @@ static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
{ .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
};
static struct freq_tbl clk_tbl_cam[] = {
static const struct freq_tbl clk_tbl_cam[] = {
{ 6000000, P_PLL8, 4, 1, 16 },
{ 8000000, P_PLL8, 4, 1, 12 },
{ 12000000, P_PLL8, 4, 1, 8 },
@@ -323,7 +323,7 @@ static struct clk_branch camclk2_clk = {
};
static struct freq_tbl clk_tbl_csi[] = {
static const struct freq_tbl clk_tbl_csi[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
@@ -715,7 +715,7 @@ static struct clk_pix_rdi csi_rdi2_clk = {
},
};
static struct freq_tbl clk_tbl_csiphytimer[] = {
static const struct freq_tbl clk_tbl_csiphytimer[] = {
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
{ }
@@ -808,7 +808,7 @@ static struct clk_branch csiphy2_timer_clk = {
},
};
static struct freq_tbl clk_tbl_gfx2d[] = {
static const struct freq_tbl clk_tbl_gfx2d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -948,7 +948,7 @@ static struct clk_branch gfx2d1_clk = {
},
};
static struct freq_tbl clk_tbl_gfx3d[] = {
static const struct freq_tbl clk_tbl_gfx3d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -968,7 +968,7 @@ static struct freq_tbl clk_tbl_gfx3d[] = {
{ }
};
static struct freq_tbl clk_tbl_gfx3d_8064[] = {
static const struct freq_tbl clk_tbl_gfx3d_8064[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -1058,7 +1058,7 @@ static struct clk_branch gfx3d_clk = {
},
};
static struct freq_tbl clk_tbl_vcap[] = {
static const struct freq_tbl clk_tbl_vcap[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 54860000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
@@ -1149,7 +1149,7 @@ static struct clk_branch vcap_npl_clk = {
},
};
static struct freq_tbl clk_tbl_ijpeg[] = {
static const struct freq_tbl clk_tbl_ijpeg[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },
{ 54860000, P_PLL8, 7, 0, 0 },
@@ -1214,7 +1214,7 @@ static struct clk_branch ijpeg_clk = {
},
};
static struct freq_tbl clk_tbl_jpegd[] = {
static const struct freq_tbl clk_tbl_jpegd[] = {
{ 64000000, P_PLL8, 6 },
{ 76800000, P_PLL8, 5 },
{ 96000000, P_PLL8, 4 },
@@ -1264,7 +1264,7 @@ static struct clk_branch jpegd_clk = {
},
};
static struct freq_tbl clk_tbl_mdp[] = {
static const struct freq_tbl clk_tbl_mdp[] = {
{ 9600000, P_PLL8, 1, 1, 40 },
{ 13710000, P_PLL8, 1, 1, 28 },
{ 27000000, P_PXO, 1, 0, 0 },
@@ -1381,7 +1381,7 @@ static struct clk_branch mdp_vsync_clk = {
},
};
static struct freq_tbl clk_tbl_rot[] = {
static const struct freq_tbl clk_tbl_rot[] = {
{ 27000000, P_PXO, 1 },
{ 29540000, P_PLL8, 13 },
{ 32000000, P_PLL8, 12 },
@@ -1461,7 +1461,7 @@ static const struct clk_parent_data mmcc_pxo_hdmi[] = {
{ .fw_name = "hdmipll", .name = "hdmi_pll" },
};
static struct freq_tbl clk_tbl_tv[] = {
static const struct freq_tbl clk_tbl_tv[] = {
{ .src = P_HDMI_PLL, .pre_div = 1 },
{ }
};
@@ -1624,7 +1624,7 @@ static struct clk_branch hdmi_app_clk = {
},
};
static struct freq_tbl clk_tbl_vcodec[] = {
static const struct freq_tbl clk_tbl_vcodec[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 32000000, P_PLL8, 1, 12),
F_MN( 48000000, P_PLL8, 1, 8),
@@ -1699,7 +1699,7 @@ static struct clk_branch vcodec_clk = {
},
};
static struct freq_tbl clk_tbl_vpe[] = {
static const struct freq_tbl clk_tbl_vpe[] = {
{ 27000000, P_PXO, 1 },
{ 34909000, P_PLL8, 11 },
{ 38400000, P_PLL8, 10 },
@@ -1752,7 +1752,7 @@ static struct clk_branch vpe_clk = {
},
};
static struct freq_tbl clk_tbl_vfe[] = {
static const struct freq_tbl clk_tbl_vfe[] = {
{ 13960000, P_PLL8, 1, 2, 55 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },

52
drivers/clk/qcom/mmcc-msm8974.c
View File

@@ -268,7 +268,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
},
};
static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
static const struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
@@ -280,7 +280,7 @@ static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
{ }
};
static struct freq_tbl ftbl_mmss_axi_clk[] = {
static const struct freq_tbl ftbl_mmss_axi_clk[] = {
F( 19200000, P_XO, 1, 0, 0),
F( 37500000, P_GPLL0, 16, 0, 0),
F( 50000000, P_GPLL0, 12, 0, 0),
@@ -306,7 +306,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
},
};
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
F( 19200000, P_XO, 1, 0, 0),
F( 37500000, P_GPLL0, 16, 0, 0),
F( 50000000, P_GPLL0, 12, 0, 0),
@@ -331,7 +331,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
},
};
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -389,7 +389,7 @@ static struct clk_rcg2 csi3_clk_src = {
},
};
static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
static const struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
@@ -406,7 +406,7 @@ static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
{ }
};
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
@@ -449,7 +449,7 @@ static struct clk_rcg2 vfe1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
static const struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@@ -461,7 +461,7 @@ static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
{ }
};
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@@ -490,7 +490,7 @@ static struct clk_rcg2 mdp_clk_src = {
},
};
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -567,7 +567,7 @@ static struct clk_rcg2 pclk1_clk_src = {
},
};
static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
static const struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
F(66700000, P_GPLL0, 9, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
@@ -575,7 +575,7 @@ static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
{ }
};
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_MMPLL0, 6, 0, 0),
@@ -599,7 +599,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
},
};
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -617,7 +617,7 @@ static struct clk_rcg2 cci_clk_src = {
},
};
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
@@ -655,14 +655,14 @@ static struct clk_rcg2 camss_gp1_clk_src = {
},
};
static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
static const struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(66670000, P_GPLL0, 9, 0, 0),
{ }
};
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
@@ -729,7 +729,7 @@ static struct clk_rcg2 mclk3_clk_src = {
},
};
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -774,7 +774,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
},
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
static const struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
@@ -783,7 +783,7 @@ static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
{ }
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
@@ -805,7 +805,7 @@ static struct clk_rcg2 cpp_clk_src = {
},
};
static struct freq_tbl byte_freq_tbl[] = {
static const struct freq_tbl byte_freq_tbl[] = {
{ .src = P_DSI0PLL_BYTE },
{ }
};
@@ -838,7 +838,7 @@ static struct clk_rcg2 byte1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -856,7 +856,7 @@ static struct clk_rcg2 edpaux_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
F(135000000, P_EDPLINK, 2, 0, 0),
F(270000000, P_EDPLINK, 11, 0, 0),
{ }
@@ -876,7 +876,7 @@ static struct clk_rcg2 edplink_clk_src = {
},
};
static struct freq_tbl edp_pixel_freq_tbl[] = {
static const struct freq_tbl edp_pixel_freq_tbl[] = {
{ .src = P_EDPVCO },
{ }
};
@@ -895,7 +895,7 @@ static struct clk_rcg2 edppixel_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -926,7 +926,7 @@ static struct clk_rcg2 esc1_clk_src = {
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
static const struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
@@ -945,7 +945,7 @@ static struct clk_rcg2 extpclk_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -963,7 +963,7 @@ static struct clk_rcg2 hdmi_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

8
drivers/clk/qcom/mmcc-msm8994.c
View File

@@ -974,7 +974,7 @@ static struct clk_rcg2 byte1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -1005,7 +1005,7 @@ static struct clk_rcg2 esc1_clk_src = {
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
static const struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
@@ -1024,7 +1024,7 @@ static struct clk_rcg2 extpclk_clk_src = {
},
};
static struct freq_tbl ftbl_hdmi_clk_src[] = {
static const struct freq_tbl ftbl_hdmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -1042,7 +1042,7 @@ static struct clk_rcg2 hdmi_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

8
drivers/clk/qcom/mmcc-msm8996.c
View File

@@ -734,7 +734,7 @@ static struct clk_rcg2 mdp_clk_src = {
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
static const struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
@@ -753,7 +753,7 @@ static struct clk_rcg2 extpclk_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -771,7 +771,7 @@ static struct clk_rcg2 vsync_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -815,7 +815,7 @@ static struct clk_rcg2 byte1_clk_src = {
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};

4
drivers/clk/qcom/videocc-sm8550.c
View File

@@ -449,7 +449,7 @@ static struct gdsc video_cc_mvs0_gdsc = {
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0c_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,
};
static struct gdsc video_cc_mvs1c_gdsc = {
@@ -474,7 +474,7 @@ static struct gdsc video_cc_mvs1_gdsc = {
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs1c_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,
};
static struct clk_regmap *video_cc_sm8550_clocks[] = {

5
include/dt-bindings/clock/qcom,gcc-msm8998.h
View File

@@ -193,10 +193,15 @@
#define GCC_MMSS_GPLL0_DIV_CLK 184
#define GCC_GPU_GPLL0_DIV_CLK 185
#define GCC_GPU_GPLL0_CLK 186
#define HLOS1_VOTE_LPASS_CORE_SMMU_CLK 187
#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 188
#define GCC_MSS_Q6_BIMC_AXI_CLK 189
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
#define USB_30_GDSC 2
#define LPASS_ADSP_GDSC 3
#define LPASS_CORE_GDSC 4
#define GCC_BLSP1_QUP1_BCR 0
#define GCC_BLSP1_QUP2_BCR 1

5
include/dt-bindings/clock/qcom,gcc-sc8180x.h
View File

@@ -248,6 +248,7 @@
#define GCC_USB3_SEC_CLKREF_CLK 238
#define GCC_UFS_MEM_CLKREF_EN 239
#define GCC_UFS_CARD_CLKREF_EN 240
#define GPLL9 241
#define GCC_EMAC_BCR 0
#define GCC_GPU_BCR 1
@@ -294,6 +295,10 @@
#define GCC_VIDEO_AXI0_CLK_BCR 42
#define GCC_VIDEO_AXI1_CLK_BCR 43
#define GCC_USB3_DP_PHY_SEC_BCR 44
#define GCC_USB3_UNIPHY_MP0_BCR 45
#define GCC_USB3_UNIPHY_MP1_BCR 46
#define GCC_USB3UNIPHY_PHY_MP0_BCR 47
#define GCC_USB3UNIPHY_PHY_MP1_BCR 48
/* GCC GDSCRs */
#define EMAC_GDSC 0

106
include/dt-bindings/clock/qcom,sm4450-camcc.h Normal file
View File

@@ -0,0 +1,106 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_AREG_CLK 1
#define CAM_CC_BPS_CLK 2
#define CAM_CC_BPS_CLK_SRC 3
#define CAM_CC_CAMNOC_ATB_CLK 4
#define CAM_CC_CAMNOC_AXI_CLK 5
#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
#define CAM_CC_CAMNOC_AXI_HF_CLK 7
#define CAM_CC_CAMNOC_AXI_SF_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPHY_RX_CLK_SRC 15
#define CAM_CC_CRE_AHB_CLK 16
#define CAM_CC_CRE_CLK 17
#define CAM_CC_CRE_CLK_SRC 18
#define CAM_CC_CSI0PHYTIMER_CLK 19
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
#define CAM_CC_CSI1PHYTIMER_CLK 21
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
#define CAM_CC_CSI2PHYTIMER_CLK 23
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
#define CAM_CC_CSIPHY0_CLK 25
#define CAM_CC_CSIPHY1_CLK 26
#define CAM_CC_CSIPHY2_CLK 27
#define CAM_CC_FAST_AHB_CLK_SRC 28
#define CAM_CC_ICP_ATB_CLK 29
#define CAM_CC_ICP_CLK 30
#define CAM_CC_ICP_CLK_SRC 31
#define CAM_CC_ICP_CTI_CLK 32
#define CAM_CC_ICP_TS_CLK 33
#define CAM_CC_MCLK0_CLK 34
#define CAM_CC_MCLK0_CLK_SRC 35
#define CAM_CC_MCLK1_CLK 36
#define CAM_CC_MCLK1_CLK_SRC 37
#define CAM_CC_MCLK2_CLK 38
#define CAM_CC_MCLK2_CLK_SRC 39
#define CAM_CC_MCLK3_CLK 40
#define CAM_CC_MCLK3_CLK_SRC 41
#define CAM_CC_OPE_0_AHB_CLK 42
#define CAM_CC_OPE_0_AREG_CLK 43
#define CAM_CC_OPE_0_CLK 44
#define CAM_CC_OPE_0_CLK_SRC 45
#define CAM_CC_PLL0 46
#define CAM_CC_PLL0_OUT_EVEN 47
#define CAM_CC_PLL0_OUT_ODD 48
#define CAM_CC_PLL1 49
#define CAM_CC_PLL1_OUT_EVEN 50
#define CAM_CC_PLL2 51
#define CAM_CC_PLL2_OUT_EVEN 52
#define CAM_CC_PLL3 53
#define CAM_CC_PLL3_OUT_EVEN 54
#define CAM_CC_PLL4 55
#define CAM_CC_PLL4_OUT_EVEN 56
#define CAM_CC_SLOW_AHB_CLK_SRC 57
#define CAM_CC_SOC_AHB_CLK 58
#define CAM_CC_SYS_TMR_CLK 59
#define CAM_CC_TFE_0_AHB_CLK 60
#define CAM_CC_TFE_0_CLK 61
#define CAM_CC_TFE_0_CLK_SRC 62
#define CAM_CC_TFE_0_CPHY_RX_CLK 63
#define CAM_CC_TFE_0_CSID_CLK 64
#define CAM_CC_TFE_0_CSID_CLK_SRC 65
#define CAM_CC_TFE_1_AHB_CLK 66
#define CAM_CC_TFE_1_CLK 67
#define CAM_CC_TFE_1_CLK_SRC 68
#define CAM_CC_TFE_1_CPHY_RX_CLK 69
#define CAM_CC_TFE_1_CSID_CLK 70
#define CAM_CC_TFE_1_CSID_CLK_SRC 71
/* CAM_CC power domains */
#define CAM_CC_CAMSS_TOP_GDSC 0
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CAMSS_TOP_BCR 2
#define CAM_CC_CCI_0_BCR 3
#define CAM_CC_CCI_1_BCR 4
#define CAM_CC_CPAS_BCR 5
#define CAM_CC_CRE_BCR 6
#define CAM_CC_CSI0PHY_BCR 7
#define CAM_CC_CSI1PHY_BCR 8
#define CAM_CC_CSI2PHY_BCR 9
#define CAM_CC_ICP_BCR 10
#define CAM_CC_MCLK0_BCR 11
#define CAM_CC_MCLK1_BCR 12
#define CAM_CC_MCLK2_BCR 13
#define CAM_CC_MCLK3_BCR 14
#define CAM_CC_OPE_0_BCR 15
#define CAM_CC_TFE_0_BCR 16
#define CAM_CC_TFE_1_BCR 17
#endif

51
include/dt-bindings/clock/qcom,sm4450-dispcc.h Normal file
View File

@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_AHB1_CLK 0
#define DISP_CC_MDSS_AHB_CLK 1
#define DISP_CC_MDSS_AHB_CLK_SRC 2
#define DISP_CC_MDSS_BYTE0_CLK 3
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
#define DISP_CC_MDSS_ESC0_CLK 7
#define DISP_CC_MDSS_ESC0_CLK_SRC 8
#define DISP_CC_MDSS_MDP1_CLK 9
#define DISP_CC_MDSS_MDP_CLK 10
#define DISP_CC_MDSS_MDP_CLK_SRC 11
#define DISP_CC_MDSS_MDP_LUT1_CLK 12
#define DISP_CC_MDSS_MDP_LUT_CLK 13
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14
#define DISP_CC_MDSS_PCLK0_CLK 15
#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
#define DISP_CC_MDSS_ROT1_CLK 17
#define DISP_CC_MDSS_ROT_CLK 18
#define DISP_CC_MDSS_ROT_CLK_SRC 19
#define DISP_CC_MDSS_RSCC_AHB_CLK 20
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21
#define DISP_CC_MDSS_VSYNC1_CLK 22
#define DISP_CC_MDSS_VSYNC_CLK 23
#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
#define DISP_CC_PLL0 25
#define DISP_CC_PLL1 26
#define DISP_CC_SLEEP_CLK 27
#define DISP_CC_SLEEP_CLK_SRC 28
#define DISP_CC_XO_CLK 29
#define DISP_CC_XO_CLK_SRC 30
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
#define DISP_CC_MDSS_CORE_INT2_GDSC 1
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
#endif

62
include/dt-bindings/clock/qcom,sm4450-gpucc.h Normal file
View File

@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GFX3D_SLV_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_DEMET_CLK 10
#define GPU_CC_DEMET_DIV_CLK_SRC 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_FREQ_MEASURE_CLK 13
#define GPU_CC_GMU_CLK_SRC 14
#define GPU_CC_GX_CXO_CLK 15
#define GPU_CC_GX_FF_CLK 16
#define GPU_CC_GX_GFX3D_CLK 17
#define GPU_CC_GX_GFX3D_CLK_SRC 18
#define GPU_CC_GX_GFX3D_RDVM_CLK 19
#define GPU_CC_GX_GMU_CLK 20
#define GPU_CC_GX_VSENSE_CLK 21
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 22
#define GPU_CC_HUB_AON_CLK 23
#define GPU_CC_HUB_CLK_SRC 24
#define GPU_CC_HUB_CX_INT_CLK 25
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 26
#define GPU_CC_MEMNOC_GFX_CLK 27
#define GPU_CC_MND1X_0_GFX3D_CLK 28
#define GPU_CC_PLL0 29
#define GPU_CC_PLL1 30
#define GPU_CC_SLEEP_CLK 31
#define GPU_CC_XO_CLK_SRC 32
#define GPU_CC_XO_DIV_CLK_SRC 33
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
/* GPU_CC resets */
#define GPU_CC_ACD_BCR 0
#define GPU_CC_CB_BCR 1
#define GPU_CC_CX_BCR 2
#define GPU_CC_FAST_HUB_BCR 3
#define GPU_CC_FF_BCR 4
#define GPU_CC_GFX3D_AON_BCR 5
#define GPU_CC_GMU_BCR 6
#define GPU_CC_GX_BCR 7
#define GPU_CC_XO_BCR 8
#define GPU_CC_GX_ACD_IROOT_BCR 9
#define GPU_CC_RBCPR_BCR 10
#endif

135
include/dt-bindings/clock/qcom,sm8150-camcc.h Normal file
View File

@@ -0,0 +1,135 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL2_OUT_MAIN 6
#define CAM_CC_PLL3 7
#define CAM_CC_PLL3_OUT_EVEN 8
#define CAM_CC_PLL4 9
#define CAM_CC_PLL4_OUT_EVEN 10
#define CAM_CC_BPS_AHB_CLK 11
#define CAM_CC_BPS_AREG_CLK 12
#define CAM_CC_BPS_AXI_CLK 13
#define CAM_CC_BPS_CLK 14
#define CAM_CC_BPS_CLK_SRC 15
#define CAM_CC_CAMNOC_AXI_CLK 16
#define CAM_CC_CAMNOC_AXI_CLK_SRC 17
#define CAM_CC_CAMNOC_DCD_XO_CLK 18
#define CAM_CC_CCI_0_CLK 19
#define CAM_CC_CCI_0_CLK_SRC 20
#define CAM_CC_CCI_1_CLK 21
#define CAM_CC_CCI_1_CLK_SRC 22
#define CAM_CC_CORE_AHB_CLK 23
#define CAM_CC_CPAS_AHB_CLK 24
#define CAM_CC_CPHY_RX_CLK_SRC 25
#define CAM_CC_CSI0PHYTIMER_CLK 26
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 27
#define CAM_CC_CSI1PHYTIMER_CLK 28
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 29
#define CAM_CC_CSI2PHYTIMER_CLK 30
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 31
#define CAM_CC_CSI3PHYTIMER_CLK 32
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 33
#define CAM_CC_CSIPHY0_CLK 34
#define CAM_CC_CSIPHY1_CLK 35
#define CAM_CC_CSIPHY2_CLK 36
#define CAM_CC_CSIPHY3_CLK 37
#define CAM_CC_FAST_AHB_CLK_SRC 38
#define CAM_CC_FD_CORE_CLK 39
#define CAM_CC_FD_CORE_CLK_SRC 40
#define CAM_CC_FD_CORE_UAR_CLK 41
#define CAM_CC_GDSC_CLK 42
#define CAM_CC_ICP_AHB_CLK 43
#define CAM_CC_ICP_CLK 44
#define CAM_CC_ICP_CLK_SRC 45
#define CAM_CC_IFE_0_AXI_CLK 46
#define CAM_CC_IFE_0_CLK 47
#define CAM_CC_IFE_0_CLK_SRC 48
#define CAM_CC_IFE_0_CPHY_RX_CLK 49
#define CAM_CC_IFE_0_CSID_CLK 50
#define CAM_CC_IFE_0_CSID_CLK_SRC 51
#define CAM_CC_IFE_0_DSP_CLK 52
#define CAM_CC_IFE_1_AXI_CLK 53
#define CAM_CC_IFE_1_CLK 54
#define CAM_CC_IFE_1_CLK_SRC 55
#define CAM_CC_IFE_1_CPHY_RX_CLK 56
#define CAM_CC_IFE_1_CSID_CLK 57
#define CAM_CC_IFE_1_CSID_CLK_SRC 58
#define CAM_CC_IFE_1_DSP_CLK 59
#define CAM_CC_IFE_LITE_0_CLK 60
#define CAM_CC_IFE_LITE_0_CLK_SRC 61
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 62
#define CAM_CC_IFE_LITE_0_CSID_CLK 63
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 64
#define CAM_CC_IFE_LITE_1_CLK 65
#define CAM_CC_IFE_LITE_1_CLK_SRC 66
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 67
#define CAM_CC_IFE_LITE_1_CSID_CLK 68
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 69
#define CAM_CC_IPE_0_AHB_CLK 70
#define CAM_CC_IPE_0_AREG_CLK 71
#define CAM_CC_IPE_0_AXI_CLK 72
#define CAM_CC_IPE_0_CLK 73
#define CAM_CC_IPE_0_CLK_SRC 74
#define CAM_CC_IPE_1_AHB_CLK 75
#define CAM_CC_IPE_1_AREG_CLK 76
#define CAM_CC_IPE_1_AXI_CLK 77
#define CAM_CC_IPE_1_CLK 78
#define CAM_CC_JPEG_CLK 79
#define CAM_CC_JPEG_CLK_SRC 80
#define CAM_CC_LRME_CLK 81
#define CAM_CC_LRME_CLK_SRC 82
#define CAM_CC_MCLK0_CLK 83
#define CAM_CC_MCLK0_CLK_SRC 84
#define CAM_CC_MCLK1_CLK 85
#define CAM_CC_MCLK1_CLK_SRC 86
#define CAM_CC_MCLK2_CLK 87
#define CAM_CC_MCLK2_CLK_SRC 88
#define CAM_CC_MCLK3_CLK 89
#define CAM_CC_MCLK3_CLK_SRC 90
#define CAM_CC_SLOW_AHB_CLK_SRC 91
/* CAM_CC power domains */
#define TITAN_TOP_GDSC 0
#define BPS_GDSC 1
#define IFE_0_GDSC 2
#define IFE_1_GDSC 3
#define IPE_0_GDSC 4
#define IPE_1_GDSC 5
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_CCI_BCR 2
#define CAM_CC_CPAS_BCR 3
#define CAM_CC_CSI0PHY_BCR 4
#define CAM_CC_CSI1PHY_BCR 5
#define CAM_CC_CSI2PHY_BCR 6
#define CAM_CC_CSI3PHY_BCR 7
#define CAM_CC_FD_BCR 8
#define CAM_CC_ICP_BCR 9
#define CAM_CC_IFE_0_BCR 10
#define CAM_CC_IFE_1_BCR 11
#define CAM_CC_IFE_LITE_0_BCR 12
#define CAM_CC_IFE_LITE_1_BCR 13
#define CAM_CC_IPE_0_BCR 14
#define CAM_CC_IPE_1_BCR 15
#define CAM_CC_JPEG_BCR 16
#define CAM_CC_LRME_BCR 17
#define CAM_CC_MCLK0_BCR 18
#define CAM_CC_MCLK1_BCR 19
#define CAM_CC_MCLK2_BCR 20
#define CAM_CC_MCLK3_BCR 21
#endif

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include/dt-bindings/clock/qcom,sm8650-dispcc.h
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@@ -1,102 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
* Copyright (c) 2023, Linaro Ltd.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
#define DISP_CC_MDSS_ESC0_CLK 56
#define DISP_CC_MDSS_ESC0_CLK_SRC 57
#define DISP_CC_MDSS_ESC1_CLK 58
#define DISP_CC_MDSS_ESC1_CLK_SRC 59
#define DISP_CC_MDSS_MDP1_CLK 60
#define DISP_CC_MDSS_MDP_CLK 61
#define DISP_CC_MDSS_MDP_CLK_SRC 62
#define DISP_CC_MDSS_MDP_LUT1_CLK 63
#define DISP_CC_MDSS_MDP_LUT_CLK 64
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
#define DISP_CC_MDSS_PCLK0_CLK 66
#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
#define DISP_CC_MDSS_PCLK1_CLK 68
#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
#define DISP_CC_MDSS_RSCC_AHB_CLK 70
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
#define DISP_CC_MDSS_VSYNC1_CLK 72
#define DISP_CC_MDSS_VSYNC_CLK 73
#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
#define DISP_CC_PLL0 75
#define DISP_CC_PLL1 76
#define DISP_CC_SLEEP_CLK 77
#define DISP_CC_SLEEP_CLK_SRC 78
#define DISP_CC_XO_CLK 79
#define DISP_CC_XO_CLK_SRC 80
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

1
include/dt-bindings/clock/qcom,sm8650-dispcc.h Symbolic link
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qcom,sm8550-dispcc.h

46
include/dt-bindings/interconnect/qcom,ipq5332.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef INTERCONNECT_QCOM_IPQ5332_H
#define INTERCONNECT_QCOM_IPQ5332_H
#define MASTER_SNOC_PCIE3_1_M 0
#define SLAVE_SNOC_PCIE3_1_M 1
#define MASTER_ANOC_PCIE3_1_S 2
#define SLAVE_ANOC_PCIE3_1_S 3
#define MASTER_SNOC_PCIE3_2_M 4
#define SLAVE_SNOC_PCIE3_2_M 5
#define MASTER_ANOC_PCIE3_2_S 6
#define SLAVE_ANOC_PCIE3_2_S 7
#define MASTER_SNOC_USB 8
#define SLAVE_SNOC_USB 9
#define MASTER_NSSNOC_NSSCC 10
#define SLAVE_NSSNOC_NSSCC 11
#define MASTER_NSSNOC_SNOC_0 12
#define SLAVE_NSSNOC_SNOC_0 13
#define MASTER_NSSNOC_SNOC_1 14
#define SLAVE_NSSNOC_SNOC_1 15
#define MASTER_NSSNOC_ATB 16
#define SLAVE_NSSNOC_ATB 17
#define MASTER_NSSNOC_PCNOC_1 18
#define SLAVE_NSSNOC_PCNOC_1 19
#define MASTER_NSSNOC_QOSGEN_REF 20
#define SLAVE_NSSNOC_QOSGEN_REF 21
#define MASTER_NSSNOC_TIMEOUT_REF 22
#define SLAVE_NSSNOC_TIMEOUT_REF 23
#define MASTER_NSSNOC_XO_DCD 24
#define SLAVE_NSSNOC_XO_DCD 25
#define MASTER_NSSNOC_PPE 0
#define SLAVE_NSSNOC_PPE 1
#define MASTER_NSSNOC_PPE_CFG 2
#define SLAVE_NSSNOC_PPE_CFG 3
#define MASTER_NSSNOC_NSS_CSR 4
#define SLAVE_NSSNOC_NSS_CSR 5
#define MASTER_NSSNOC_CE_APB 6
#define SLAVE_NSSNOC_CE_APB 7
#define MASTER_NSSNOC_CE_AXI 8
#define SLAVE_NSSNOC_CE_AXI 9
#define MASTER_CNOC_AHB 0
#define SLAVE_CNOC_AHB 1
#endif /* INTERCONNECT_QCOM_IPQ5332_H */