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drm/amdgpu/jpeg: clean up reset type handling

Browse Source 
Make the handling consistent with other IPs and across
JPEG versions.

Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2025-07-15 11:37:56 -04:00
parent 084300fef5
commit 82a7c94fce
8 changed files with 29 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
View File

@@ -118,8 +118,10 @@ static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return r;

4
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
View File

@@ -167,8 +167,10 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return r;

4
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
View File

@@ -132,8 +132,10 @@ static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return r;

4
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
View File

@@ -143,8 +143,10 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return r;

14
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
View File

@@ -216,12 +216,11 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
if (!amdgpu_sriov_vf(adev)) {
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
if (r)
return r;
}
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return 0;
}
@@ -242,8 +241,7 @@ static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
if (!amdgpu_sriov_vf(adev))
amdgpu_jpeg_sysfs_reset_mask_fini(adev);
amdgpu_jpeg_sysfs_reset_mask_fini(adev);
r = amdgpu_jpeg_sw_fini(adev);

2
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
View File

@@ -177,7 +177,7 @@ static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
if (r)
return r;

7
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
View File

@@ -123,11 +123,10 @@ static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
if (r)
return r;
return 0;
return r;
}
/**

16
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
View File

@@ -200,14 +200,13 @@ static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
if (!amdgpu_sriov_vf(adev)) {
adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
if (r)
return r;
}
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return 0;
return r;
}
/**
@@ -226,8 +225,7 @@ static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
if (!amdgpu_sriov_vf(adev))
amdgpu_jpeg_sysfs_reset_mask_fini(adev);
amdgpu_jpeg_sysfs_reset_mask_fini(adev);
r = amdgpu_jpeg_sw_fini(adev);