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drm/amdgpu: Release SDMAv4.4.2 ecc irq properly

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Release ECC irq only if irq is enabled - only when RAS feature is enabled
ECC irq gets enabled.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
2023-06-13 16:05:21 +05:30
committed by Alex Deucher
parent d4a4ff1c8e
commit 82a1f42f6a
1 changed files with 10 additions and 6 deletions
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16
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
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@@ -1434,9 +1434,11 @@ static int sdma_v4_4_2_hw_fini(void *handle)
return 0;
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
for (i = 0; i < adev->sdma.num_instances; i++) {
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
for (i = 0; i < adev->sdma.num_instances; i++) {
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
}
}
sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
@@ -2073,9 +2075,11 @@ static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
uint32_t tmp_mask = inst_mask;
int i;
for_each_inst(i, tmp_mask) {
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
for_each_inst(i, tmp_mask) {
amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0 + i);
}
}
sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);