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drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate

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We are currently having FIFO underruns happening for kms_dsc test case,
problem is that, we check if curreny cdclk is >= pixel rate only if
there is a single VDSC engine enabled(i.e dsc_split=false) however if
we happen to have 2 VDSC engines enabled, we just kinda rely that this
would be automatically enough.
However pixel rate can be even >= than VDSC clock(cdclk) * 2, so in that
case even with 2 VDSC engines enabled, we still need to tweak it up.
So lets compare pixel rate with cdclk * VDSC engine count and
check if it still requires bumping up.
Previously we had to bump up CDCLK many times for similar reasons.

v2: - Use new intel_dsc_get_num_vdsc_instances to determine number of VDSC
      engines, instead of slice count(Ankit Nautiyal)
v3: - s/u8/int/ (Jani Nikula)
v4: - Remove slice count mentions(Ankit Nautiyal)
    - Use DIV_ROUND_UP in order to make sure that resulting CDCLK would
      be always >= than required, after division(Ankit Nautiyal)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230704131758.14024-3-stanislav.lisovskiy@intel.com
This commit is contained in:
Stanislav Lisovskiy
2023-07-04 16:17:58 +03:00
parent 08a3a79ef8
commit 8290bcee57
1 changed files with 10 additions and 2 deletions
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12
drivers/gpu/drm/i915/display/intel_cdclk.c
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@@ -37,6 +37,7 @@
#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "vlv_sideband.h"
/**
@@ -2607,9 +2608,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
* When we decide to use only one VDSC engine, since
* each VDSC operates with 1 ppc throughput, pixel clock
* cannot be higher than the VDSC clock (cdclk)
* If there 2 VDSC engines, then pixel clock can't be higher than
* VDSC clock(cdclk) * 2 and so on.
*/
if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
if (crtc_state->dsc.compression_enable) {
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
min_cdclk = max_t(int, min_cdclk,
DIV_ROUND_UP(crtc_state->pixel_rate,
num_vdsc_instances));
}
/*
* HACK. Currently for TGL/DG2 platforms we calculate