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mips: dts: ralink: mt7621: reorder serial0 properties

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Reorder serial0 properties according to the guidelines laid
out in Documentation/devicetree/bindings/dts-coding-style.rst

Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Justin Swartz
2024-03-08 17:56:15 +02:00
committed by Thomas Bogendoerfer
parent bc75dffadc
commit 82394085bf
1 changed files with 3 additions and 2 deletions
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5
arch/mips/boot/dts/ralink/mt7621.dtsi
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@@ -115,13 +115,14 @@ serial0: serial@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&sysc MT7621_CLK_UART1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test;
pinctrl-names = "default";