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ASoC: fsl_utils: Add function to constrain rates
Platforms like i.MX93/91 only have one audio PLL. Some sample rates are not supported. Add common function to constrain rates according to different clock sources. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Link: https://patch.msgid.link/20241126115440.3929061-2-chancel.liu@nxp.com Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@@ -152,6 +152,51 @@ void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
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}
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EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
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/**
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* fsl_asoc_constrain_rates - constrain rates according to clocks
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*
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* @target_constr: target constraint
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* @original_constr: original constraint
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* @pll8k_clk: PLL clock pointer for 8kHz
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* @pll11k_clk: PLL clock pointer for 11kHz
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* @ext_clk: External clock pointer
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* @target_rates: target rates array
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*
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* This function constrain rates according to clocks
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*/
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void fsl_asoc_constrain_rates(struct snd_pcm_hw_constraint_list *target_constr,
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const struct snd_pcm_hw_constraint_list *original_constr,
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struct clk *pll8k_clk, struct clk *pll11k_clk,
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struct clk *ext_clk, int *target_rates)
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{
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int i, j, k = 0;
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u64 clk_rate[3];
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*target_constr = *original_constr;
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if (pll8k_clk || pll11k_clk || ext_clk) {
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target_constr->list = target_rates;
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target_constr->count = 0;
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for (i = 0; i < original_constr->count; i++) {
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clk_rate[0] = clk_get_rate(pll8k_clk);
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clk_rate[1] = clk_get_rate(pll11k_clk);
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clk_rate[2] = clk_get_rate(ext_clk);
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for (j = 0; j < 3; j++) {
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if (clk_rate[j] != 0 &&
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do_div(clk_rate[j], original_constr->list[i]) == 0) {
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target_rates[k++] = original_constr->list[i];
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target_constr->count++;
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break;
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}
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}
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}
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/* protection for if there is no proper rate found*/
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if (!target_constr->count)
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*target_constr = *original_constr;
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}
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}
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EXPORT_SYMBOL(fsl_asoc_constrain_rates);
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MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
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MODULE_DESCRIPTION("Freescale ASoC utility code");
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MODULE_LICENSE("GPL v2");
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@@ -26,4 +26,9 @@ void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
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void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
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struct clk *pll8k_clk,
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struct clk *pll11k_clk, u64 ratio);
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void fsl_asoc_constrain_rates(struct snd_pcm_hw_constraint_list *target_constr,
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const struct snd_pcm_hw_constraint_list *original_constr,
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struct clk *pll8k_clk, struct clk *pll11k_clk,
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struct clk *ext_clk, int *target_rates);
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#endif /* _FSL_UTILS_H */
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