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drm/amd/display: Add DCN35 DCCG
[Why & How] Add DCCG handling for DCN35. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Qingqing Zhuo
committed by
Alex Deucher
Alex Deucher
parent
5f0326ea95
commit
819af8dc9a
737
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
Normal file
737
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
Normal file
@@ -0,0 +1,737 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn35_dccg.h"
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#define TO_DCN_DCCG(dccg)\
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container_of(dccg, struct dcn_dccg, base)
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#define REG(reg) \
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(dccg_dcn->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
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#define CTX \
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dccg_dcn->base.ctx
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#define DC_LOGGER \
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dccg->ctx->logger
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static void dcn35_set_dppclk_enable(struct dccg *dccg,
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uint32_t dpp_inst, uint32_t enable)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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switch (dpp_inst) {
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case 0:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);
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break;
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case 1:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);
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break;
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case 2:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);
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break;
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case 3:
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REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);
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break;
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default:
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break;
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}
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}
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static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,
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int req_dppclk)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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if (dccg->dpp_clock_gated[dpp_inst]) {
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/*
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* Do not update the DPPCLK DTO if the clock is stopped.
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*/
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return;
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}
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if (dccg->ref_dppclk && req_dppclk) {
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int ref_dppclk = dccg->ref_dppclk;
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int modulo, phase;
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// phase / modulo = dpp pipe clk / dpp global clk
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modulo = 0xff; // use FF at the end
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phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
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if (phase > 0xff) {
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ASSERT(false);
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phase = 0xff;
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}
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REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
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DPPCLK0_DTO_PHASE, phase,
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DPPCLK0_DTO_MODULO, modulo);
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dcn35_set_dppclk_enable(dccg, dpp_inst, true);
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} else
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dcn35_set_dppclk_enable(dccg, dpp_inst, false);
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dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
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}
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static void dccg35_get_pixel_rate_div(
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struct dccg *dccg,
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uint32_t otg_inst,
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enum pixel_rate_div *k1,
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enum pixel_rate_div *k2)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;
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*k1 = PIXEL_RATE_DIV_NA;
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*k2 = PIXEL_RATE_DIV_NA;
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switch (otg_inst) {
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case 0:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG0_PIXEL_RATE_DIVK1, &val_k1,
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OTG0_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 1:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG1_PIXEL_RATE_DIVK1, &val_k1,
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OTG1_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 2:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG2_PIXEL_RATE_DIVK1, &val_k1,
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OTG2_PIXEL_RATE_DIVK2, &val_k2);
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break;
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case 3:
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REG_GET_2(OTG_PIXEL_RATE_DIV,
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OTG3_PIXEL_RATE_DIVK1, &val_k1,
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OTG3_PIXEL_RATE_DIVK2, &val_k2);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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*k1 = (enum pixel_rate_div)val_k1;
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*k2 = (enum pixel_rate_div)val_k2;
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}
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static void dccg35_set_pixel_rate_div(
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struct dccg *dccg,
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uint32_t otg_inst,
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enum pixel_rate_div k1,
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enum pixel_rate_div k2)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA;
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// Don't program 0xF into the register field. Not valid since
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// K1 / K2 field is only 1 / 2 bits wide
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if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {
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BREAK_TO_DEBUGGER();
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return;
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}
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dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);
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if (k1 == cur_k1 && k2 == cur_k2)
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return;
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switch (otg_inst) {
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case 0:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG0_PIXEL_RATE_DIVK1, k1,
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OTG0_PIXEL_RATE_DIVK2, k2);
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break;
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case 1:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG1_PIXEL_RATE_DIVK1, k1,
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OTG1_PIXEL_RATE_DIVK2, k2);
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break;
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case 2:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG2_PIXEL_RATE_DIVK1, k1,
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OTG2_PIXEL_RATE_DIVK2, k2);
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break;
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case 3:
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REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
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OTG3_PIXEL_RATE_DIVK1, k1,
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OTG3_PIXEL_RATE_DIVK2, k2);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg35_set_dtbclk_p_src(
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struct dccg *dccg,
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enum streamclk_source src,
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uint32_t otg_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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uint32_t p_src_sel = 0; /* selects dprefclk */
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if (src == DTBCLK0)
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p_src_sel = 2; /* selects dtbclk0 */
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switch (otg_inst) {
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case 0:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P0_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P0_SRC_SEL, p_src_sel,
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DTBCLK_P0_EN, 1);
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break;
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case 1:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P1_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P1_SRC_SEL, p_src_sel,
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DTBCLK_P1_EN, 1);
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break;
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case 2:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P2_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P2_SRC_SEL, p_src_sel,
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DTBCLK_P2_EN, 1);
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break;
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case 3:
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if (src == REFCLK)
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REG_UPDATE(DTBCLK_P_CNTL,
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DTBCLK_P3_EN, 0);
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else
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REG_UPDATE_2(DTBCLK_P_CNTL,
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DTBCLK_P3_SRC_SEL, p_src_sel,
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DTBCLK_P3_EN, 1);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
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static void dccg35_set_dtbclk_dto(
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struct dccg *dccg,
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const struct dtbclk_dto_params *params)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* DTO Output Rate / Pixel Rate = 1/4 */
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int req_dtbclk_khz = params->pixclk_khz / 4;
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if (params->ref_dtbclk_khz && req_dtbclk_khz) {
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uint32_t modulo, phase;
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// phase / modulo = dtbclk / dtbclk ref
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modulo = params->ref_dtbclk_khz * 1000;
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phase = req_dtbclk_khz * 1000;
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REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
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REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLK_DTO_ENABLE[params->otg_inst], 1);
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REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
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1, 100);
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/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
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dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
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/* The recommended programming sequence to enable DTBCLK DTO to generate
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* valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
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* be set only after DTO is enabled
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*/
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REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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PIPE_DTO_SRC_SEL[params->otg_inst], 2);
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} else {
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REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
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DTBCLK_DTO_ENABLE[params->otg_inst], 0,
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PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);
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REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
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REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
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}
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}
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static void dccg35_set_dpstreamclk(
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struct dccg *dccg,
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enum streamclk_source src,
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int otg_inst,
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int dp_hpo_inst)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* set the dtbclk_p source */
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dccg35_set_dtbclk_p_src(dccg, src, otg_inst);
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/* enabled to select one of the DTBCLKs for pipe */
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switch (dp_hpo_inst) {
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case 0:
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REG_UPDATE_2(DPSTREAMCLK_CNTL,
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DPSTREAMCLK0_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);
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break;
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case 1:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);
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break;
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case 2:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);
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break;
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case 3:
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REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
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(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);
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break;
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default:
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BREAK_TO_DEBUGGER();
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return;
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}
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}
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static void dccg35_set_physymclk(
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struct dccg *dccg,
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int phy_inst,
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enum physymclk_clock_source clk_src,
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bool force_enable)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */
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switch (phy_inst) {
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case 0:
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if (force_enable) {
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REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
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PHYASYMCLK_EN, 1,
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PHYASYMCLK_SRC_SEL, clk_src);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYASYMCLK_ROOT_GATE_DISABLE, 1);
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} else {
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REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
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PHYASYMCLK_EN, 0,
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PHYASYMCLK_SRC_SEL, 0);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYASYMCLK_ROOT_GATE_DISABLE, 0);
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}
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break;
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case 1:
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if (force_enable) {
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REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
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PHYBSYMCLK_EN, 1,
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PHYBSYMCLK_SRC_SEL, clk_src);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYBSYMCLK_ROOT_GATE_DISABLE, 1);
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} else {
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REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
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PHYBSYMCLK_EN, 0,
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PHYBSYMCLK_SRC_SEL, 0);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYBSYMCLK_ROOT_GATE_DISABLE, 0);
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}
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break;
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case 2:
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if (force_enable) {
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REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
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PHYCSYMCLK_EN, 1,
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PHYCSYMCLK_SRC_SEL, clk_src);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYCSYMCLK_ROOT_GATE_DISABLE, 1);
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} else {
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REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
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PHYCSYMCLK_EN, 0,
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PHYCSYMCLK_SRC_SEL, 0);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYCSYMCLK_ROOT_GATE_DISABLE, 0);
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}
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break;
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case 3:
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if (force_enable) {
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REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
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PHYDSYMCLK_EN, 1,
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PHYDSYMCLK_SRC_SEL, clk_src);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYDSYMCLK_ROOT_GATE_DISABLE, 1);
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} else {
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REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
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PHYDSYMCLK_EN, 0,
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PHYDSYMCLK_SRC_SEL, 0);
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if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
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REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
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PHYDSYMCLK_ROOT_GATE_DISABLE, 0);
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}
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break;
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case 4:
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if (force_enable) {
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REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
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PHYESYMCLK_EN, 1,
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PHYESYMCLK_SRC_SEL, clk_src);
|
||||
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
|
||||
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
|
||||
PHYESYMCLK_ROOT_GATE_DISABLE, 1);
|
||||
} else {
|
||||
REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
|
||||
PHYESYMCLK_EN, 0,
|
||||
PHYESYMCLK_SRC_SEL, 0);
|
||||
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
|
||||
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
|
||||
PHYESYMCLK_ROOT_GATE_DISABLE, 0);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void dccg35_set_valid_pixel_rate(
|
||||
struct dccg *dccg,
|
||||
int ref_dtbclk_khz,
|
||||
int otg_inst,
|
||||
int pixclk_khz)
|
||||
{
|
||||
struct dtbclk_dto_params dto_params = {0};
|
||||
|
||||
dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
|
||||
dto_params.otg_inst = otg_inst;
|
||||
dto_params.pixclk_khz = pixclk_khz;
|
||||
dto_params.is_hdmi = true;
|
||||
|
||||
dccg35_set_dtbclk_dto(dccg, &dto_params);
|
||||
}
|
||||
|
||||
static void dccg35_dpp_root_clock_control(
|
||||
struct dccg *dccg,
|
||||
unsigned int dpp_inst,
|
||||
bool clock_on)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
|
||||
return;
|
||||
|
||||
if (clock_on) {
|
||||
/* turn off the DTO and leave phase/modulo at max */
|
||||
dcn35_set_dppclk_enable(dccg, dpp_inst, 0);
|
||||
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
|
||||
DPPCLK0_DTO_PHASE, 0xFF,
|
||||
DPPCLK0_DTO_MODULO, 0xFF);
|
||||
} else {
|
||||
dcn35_set_dppclk_enable(dccg, dpp_inst, 1);
|
||||
/* turn on the DTO to generate a 0hz clock */
|
||||
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
|
||||
DPPCLK0_DTO_PHASE, 0,
|
||||
DPPCLK0_DTO_MODULO, 1);
|
||||
}
|
||||
|
||||
dccg->dpp_clock_gated[dpp_inst] = !clock_on;
|
||||
}
|
||||
|
||||
void dccg35_init(struct dccg *dccg)
|
||||
{
|
||||
int otg_inst;
|
||||
/* Set HPO stream encoder to use refclk to avoid case where PHY is
|
||||
* disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which
|
||||
* will cause DCN to hang.
|
||||
*/
|
||||
for (otg_inst = 0; otg_inst < 4; otg_inst++)
|
||||
dccg31_disable_symclk32_se(dccg, otg_inst);
|
||||
|
||||
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
|
||||
for (otg_inst = 0; otg_inst < 2; otg_inst++)
|
||||
dccg31_disable_symclk32_le(dccg, otg_inst);
|
||||
|
||||
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
|
||||
for (otg_inst = 0; otg_inst < 4; otg_inst++)
|
||||
dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,
|
||||
otg_inst);
|
||||
|
||||
if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
|
||||
for (otg_inst = 0; otg_inst < 5; otg_inst++)
|
||||
dccg35_set_physymclk(dccg, otg_inst,
|
||||
PHYSYMCLK_FORCE_SRC_SYMCLK, false);
|
||||
/*
|
||||
dccg35_enable_global_fgcg_rep(
|
||||
dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
|
||||
.dccg_global_fgcg_rep);*/
|
||||
}
|
||||
|
||||
void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value);
|
||||
}
|
||||
|
||||
static void dccg35_enable_dscclk(struct dccg *dccg, int inst)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
//Disable DTO
|
||||
switch (inst) {
|
||||
case 0:
|
||||
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
|
||||
DSCCLK0_DTO_PHASE, 0,
|
||||
DSCCLK0_DTO_MODULO, 0);
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
|
||||
DSCCLK1_DTO_PHASE, 0,
|
||||
DSCCLK1_DTO_MODULO, 0);
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
|
||||
DSCCLK2_DTO_PHASE, 0,
|
||||
DSCCLK2_DTO_MODULO, 0);
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
|
||||
DSCCLK3_DTO_PHASE, 0,
|
||||
DSCCLK3_DTO_MODULO, 0);
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void dccg35_disable_dscclk(struct dccg *dccg,
|
||||
int inst)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
|
||||
return;
|
||||
|
||||
switch (inst) {
|
||||
case 0:
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);
|
||||
REG_UPDATE_2(DSCCLK0_DTO_PARAM,
|
||||
DSCCLK0_DTO_PHASE, 0,
|
||||
DSCCLK0_DTO_MODULO, 1);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);
|
||||
REG_UPDATE_2(DSCCLK1_DTO_PARAM,
|
||||
DSCCLK1_DTO_PHASE, 0,
|
||||
DSCCLK1_DTO_MODULO, 1);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);
|
||||
REG_UPDATE_2(DSCCLK2_DTO_PARAM,
|
||||
DSCCLK2_DTO_PHASE, 0,
|
||||
DSCCLK2_DTO_MODULO, 1);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);
|
||||
REG_UPDATE_2(DSCCLK3_DTO_PARAM,
|
||||
DSCCLK3_DTO_PHASE, 0,
|
||||
DSCCLK3_DTO_MODULO, 1);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
switch (link_enc_inst) {
|
||||
case 0:
|
||||
REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
|
||||
SYMCLKA_CLOCK_ENABLE, 1);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
|
||||
SYMCLKB_CLOCK_ENABLE, 1);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
|
||||
SYMCLKC_CLOCK_ENABLE, 1);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
|
||||
SYMCLKD_CLOCK_ENABLE, 1);
|
||||
break;
|
||||
case 4:
|
||||
REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
|
||||
SYMCLKE_CLOCK_ENABLE, 1);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (stream_enc_inst) {
|
||||
case 0:
|
||||
REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,
|
||||
SYMCLKA_FE_EN, 1,
|
||||
SYMCLKA_FE_SRC_SEL, link_enc_inst);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,
|
||||
SYMCLKB_FE_EN, 1,
|
||||
SYMCLKB_FE_SRC_SEL, link_enc_inst);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,
|
||||
SYMCLKC_FE_EN, 1,
|
||||
SYMCLKC_FE_SRC_SEL, link_enc_inst);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,
|
||||
SYMCLKD_FE_EN, 1,
|
||||
SYMCLKD_FE_SRC_SEL, link_enc_inst);
|
||||
break;
|
||||
case 4:
|
||||
REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,
|
||||
SYMCLKE_FE_EN, 1,
|
||||
SYMCLKE_FE_SRC_SEL, link_enc_inst);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
switch (stream_enc_inst) {
|
||||
case 0:
|
||||
REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
|
||||
SYMCLKA_FE_EN, 0);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
|
||||
SYMCLKB_FE_EN, 0);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
|
||||
SYMCLKC_FE_EN, 0);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
|
||||
SYMCLKD_FE_EN, 0);
|
||||
break;
|
||||
case 4:
|
||||
REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
|
||||
SYMCLKE_FE_EN, 0);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (link_enc_inst) {
|
||||
case 0:
|
||||
REG_UPDATE(SYMCLKA_CLOCK_ENABLE,
|
||||
SYMCLKA_CLOCK_ENABLE, 0);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE(SYMCLKB_CLOCK_ENABLE,
|
||||
SYMCLKB_CLOCK_ENABLE, 0);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE(SYMCLKC_CLOCK_ENABLE,
|
||||
SYMCLKC_CLOCK_ENABLE, 0);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE(SYMCLKD_CLOCK_ENABLE,
|
||||
SYMCLKD_CLOCK_ENABLE, 0);
|
||||
break;
|
||||
case 4:
|
||||
REG_UPDATE(SYMCLKE_CLOCK_ENABLE,
|
||||
SYMCLKE_CLOCK_ENABLE, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct dccg_funcs dccg35_funcs = {
|
||||
.update_dpp_dto = dccg35_update_dpp_dto,
|
||||
.dpp_root_clock_control = dccg35_dpp_root_clock_control,
|
||||
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
|
||||
.dccg_init = dccg35_init,
|
||||
.set_dpstreamclk = dccg35_set_dpstreamclk,
|
||||
.enable_symclk32_se = dccg31_enable_symclk32_se,
|
||||
.disable_symclk32_se = dccg31_disable_symclk32_se,
|
||||
.enable_symclk32_le = dccg31_enable_symclk32_le,
|
||||
.disable_symclk32_le = dccg31_disable_symclk32_le,
|
||||
.set_physymclk = dccg35_set_physymclk,
|
||||
.set_dtbclk_dto = dccg35_set_dtbclk_dto,
|
||||
.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
|
||||
.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
|
||||
.otg_add_pixel = dccg31_otg_add_pixel,
|
||||
.otg_drop_pixel = dccg31_otg_drop_pixel,
|
||||
.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
|
||||
.disable_dsc = dccg35_disable_dscclk,
|
||||
.enable_dsc = dccg35_enable_dscclk,
|
||||
.set_pixel_rate_div = dccg35_set_pixel_rate_div,
|
||||
.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,
|
||||
.enable_symclk_se = dccg35_enable_symclk_se,
|
||||
.disable_symclk_se = dccg35_disable_symclk_se,
|
||||
};
|
||||
|
||||
struct dccg *dccg35_create(
|
||||
struct dc_context *ctx,
|
||||
const struct dccg_registers *regs,
|
||||
const struct dccg_shift *dccg_shift,
|
||||
const struct dccg_mask *dccg_mask)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
|
||||
struct dccg *base;
|
||||
|
||||
if (dccg_dcn == NULL) {
|
||||
BREAK_TO_DEBUGGER();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
base = &dccg_dcn->base;
|
||||
base->ctx = ctx;
|
||||
base->funcs = &dccg35_funcs;
|
||||
|
||||
dccg_dcn->regs = regs;
|
||||
dccg_dcn->dccg_shift = dccg_shift;
|
||||
dccg_dcn->dccg_mask = dccg_mask;
|
||||
|
||||
return &dccg_dcn->base;
|
||||
}
|
||||
190
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
Normal file
190
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
Normal file
@@ -0,0 +1,190 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DCN35_DCCG_H__
|
||||
#define __DCN35_DCCG_H__
|
||||
|
||||
#include "dcn314/dcn314_dccg.h"
|
||||
|
||||
#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
|
||||
.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
|
||||
|
||||
|
||||
#define DCCG_REG_LIST_DCN35() \
|
||||
DCCG_REG_LIST_DCN314(),\
|
||||
SR(DPPCLK_CTRL),\
|
||||
SR(DCCG_GATE_DISABLE_CNTL6),\
|
||||
SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
|
||||
SR(SYMCLKA_CLOCK_ENABLE),\
|
||||
SR(SYMCLKB_CLOCK_ENABLE),\
|
||||
SR(SYMCLKC_CLOCK_ENABLE),\
|
||||
SR(SYMCLKD_CLOCK_ENABLE),\
|
||||
SR(SYMCLKE_CLOCK_ENABLE)
|
||||
|
||||
#define DCCG_MASK_SH_LIST_DCN35(mask_sh) \
|
||||
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
|
||||
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
|
||||
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
|
||||
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
|
||||
DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\
|
||||
DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\
|
||||
DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\
|
||||
DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\
|
||||
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
|
||||
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
|
||||
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
|
||||
DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\
|
||||
DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\
|
||||
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\
|
||||
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\
|
||||
DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\
|
||||
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
|
||||
DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
|
||||
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
|
||||
DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
|
||||
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
|
||||
DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
|
||||
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\
|
||||
DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
|
||||
DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
|
||||
DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
|
||||
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\
|
||||
DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
|
||||
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
|
||||
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
|
||||
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\
|
||||
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
|
||||
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
|
||||
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
|
||||
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
|
||||
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
|
||||
DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
|
||||
DCCG_SF(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, mask_sh),\
|
||||
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\
|
||||
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\
|
||||
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\
|
||||
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\
|
||||
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\
|
||||
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\
|
||||
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh)
|
||||
|
||||
struct dccg *dccg35_create(
|
||||
struct dc_context *ctx,
|
||||
const struct dccg_registers *regs,
|
||||
const struct dccg_shift *dccg_shift,
|
||||
const struct dccg_mask *dccg_mask);
|
||||
|
||||
void dccg35_init(struct dccg *dccg);
|
||||
|
||||
void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);
|
||||
|
||||
|
||||
#endif //__DCN35_DCCG_H__
|
||||
Reference in New Issue
Block a user