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Merge tag 'imx-fixes-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

Browse Source 
i.MX fixes for 5.18:

- Increase DOMAIN_MAX_CLKS in imx8m-blk-ctrl driver to fix an ISI hang
  on i.MX8MN.
- Fix spi-tx-bus-width on imx8mq-tqma8mq board.
- Fix an SGTL5000 detection issue by moving MCLK pinctrl into SGTL5000
  codec node.
- Fix spi2 pin configuration on imx8mm-venice board.
- Fix SCU clock controller's compatible property for i.MX8QM.
- Fix SAI device compatible for i.MX8MN.
- A couple of fixes from Rob to address issues in boolean properties
  and touchscreen property sizes.
- Fix OTG controller over-current configuration for imx8mm-venice-gw
  boards.
- Fix NULL but dereferenced coccicheck error in imx-weim driver.

* tag 'imx-fixes-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx: Fix imx8*-var-som touchscreen property sizes
  ARM: dts: imx: Fix boolean properties with values
  ARM: dts: imx8mm-venice-gw{71xx,72xx,73xx}: fix OTG controller OC mode
  arm64: dts: imx8mn: Fix SAI nodes
  arm64: dts: imx8mq-tqma8mq: change the spi-nor tx
  ARM: dts: imx6qdl-apalis: Fix sgtl5000 detection issue
  soc: imx: imx8m-blk-ctrl: Fix IMX8MN_DISPBLK_PD_ISI hang
  arm64: dts: imx8qm: Correct SCU clock controller's compatible property
  arm64: dts: imx8mm-venice: fix spi2 pin configuration
  bus: imx-weim: fix NULL but dereferenced coccicheck error

Link: https://lore.kernel.org/r/20220411024301.GH129381@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-04-14 22:59:53 +02:00
parent 24a4351e1c f571e9c9aa
commit 803fa58dfa
9 changed files with 26 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@@ -286,6 +286,8 @@ vgen6_reg: vgen6 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgtl5000>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_module_3v3_audio>;
VDDIO-supply = <&reg_module_3v3>;
@@ -517,8 +519,6 @@ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
@@ -811,6 +811,12 @@ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
>;
};
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@@ -146,12 +146,14 @@ &uart3 {
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
@@ -215,7 +217,7 @@ pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@@ -211,12 +211,14 @@ &uart4 {
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@@ -309,7 +311,7 @@ pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@@ -238,12 +238,14 @@ &uart4 {
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@@ -358,7 +360,7 @@ pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

10
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -293,7 +293,7 @@ spba2: spba-bus@30000000 {
ranges;
sai2: sai@30020000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
@@ -307,7 +307,7 @@ sai2: sai@30020000 {
};
sai3: sai@30030000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
@@ -321,7 +321,7 @@ sai3: sai@30030000 {
};
sai5: sai@30050000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
@@ -337,7 +337,7 @@ sai5: sai@30050000 {
};
sai6: sai@30060000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
@@ -394,7 +394,7 @@ spdif1: spdif@30090000 {
};
sai7: sai@300b0000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,

2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
View File

@@ -253,7 +253,7 @@ flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};

2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@@ -196,7 +196,7 @@ pd: imx8qx-pd {
};
clk: clock-controller {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
#clock-cells = <2>;
};

3
drivers/bus/imx-weim.c
View File

@@ -352,8 +352,7 @@ static int of_weim_notify(struct notifier_block *nb, unsigned long action,
pdev = of_find_device_by_node(rd->dn);
if (!pdev) {
dev_err(&pdev->dev,
"Could not find platform device for '%pOF'\n",
pr_err("Could not find platform device for '%pOF'\n",
rd->dn);
ret = notifier_from_errno(-EINVAL);

2
drivers/soc/imx/imx8m-blk-ctrl.c
View File

@@ -50,7 +50,7 @@ struct imx8m_blk_ctrl_domain_data {
u32 mipi_phy_rst_mask;
};
#define DOMAIN_MAX_CLKS 3
#define DOMAIN_MAX_CLKS 4
struct imx8m_blk_ctrl_domain {
struct generic_pm_domain genpd;