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drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled

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PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
wake-up scanline counting starts from vblank_start - 1. We don't know if
wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
start reading valid value right after checking the scanline. In this
scenario we wouldn't have enough time to write all registers. To tackle
this evade scanline 0 as well. As a drawback we have 1 frame delay in flip
when waking up.

v2:
  - use intel_dsb_emit_wait_dsl
  - add evasion of scanline 0 also for Panel Replay

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-11-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander
2025-02-13 08:48:01 +02:00
parent 20d6343bf4
commit 801d827d80
1 changed files with 12 additions and 0 deletions
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12
drivers/gpu/drm/i915/display/intel_dsb.c
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@@ -564,6 +564,18 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20);
int start, end;
/*
* PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
* wake-up scanline counting starts from vblank_start - 1. We don't know
* if wake-up is already ongoing when evasion starts. In worst case
* PIPEDSL could start reading valid value right after checking the
* scanline. In this scenario we wouldn't have enough time to write all
* registers. To tackle this evade scanline 0 as well. As a drawback we
* have 1 frame delay in flip when waking up.
*/
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = intel_vrr_vblank_delay(crtc_state);