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arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com
This commit is contained in:
committed by
Nishanth Menon
parent
b08bf4a5c0
commit
7ff8432c27
@@ -632,15 +632,8 @@ dpi_out: endpoint {
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};
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie0_ep {
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status = "disabled";
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};
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&pcie1_rc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&minipcie_pins_default>;
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@@ -650,10 +643,6 @@ &pcie1_rc {
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reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
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};
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&pcie1_ep {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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interrupts = <436>;
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@@ -720,6 +720,7 @@ pcie0_rc: pcie@5500000 {
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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device_type = "pci";
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status = "disabled";
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};
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pcie0_ep: pcie-ep@5500000 {
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@@ -733,6 +734,7 @@ pcie0_ep: pcie-ep@5500000 {
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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pcie1_rc: pcie@5600000 {
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@@ -753,6 +755,7 @@ pcie1_rc: pcie@5600000 {
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x10000 0x10000>;
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device_type = "pci";
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status = "disabled";
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};
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pcie1_ep: pcie-ep@5600000 {
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@@ -766,6 +769,7 @@ pcie1_ep: pcie-ep@5600000 {
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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mcasp0: mcasp@2b00000 {
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@@ -415,22 +415,6 @@ &serdes1 {
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status = "disabled";
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};
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&pcie0_rc {
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status = "disabled";
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};
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&pcie0_ep {
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status = "disabled";
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};
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&pcie1_rc {
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status = "disabled";
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};
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&pcie1_ep {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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interrupts = <436>;
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