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drm/i915/lvds: s/pipe_config/crtc_state/
Call the crtc state 'crtc_state' rather than 'pipe_config', as is the modern style. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230130180540.8972-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
@@ -121,13 +121,13 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
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}
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static void intel_lvds_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
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u32 tmp, flags = 0;
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pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
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crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
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tmp = intel_de_read(dev_priv, lvds_encoder->reg);
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if (tmp & LVDS_HSYNC_POLARITY)
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@@ -139,20 +139,20 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
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else
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flags |= DRM_MODE_FLAG_PVSYNC;
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pipe_config->hw.adjusted_mode.flags |= flags;
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crtc_state->hw.adjusted_mode.flags |= flags;
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if (DISPLAY_VER(dev_priv) < 5)
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pipe_config->gmch_pfit.lvds_border_bits =
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crtc_state->gmch_pfit.lvds_border_bits =
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tmp & LVDS_BORDER_ENABLE;
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/* gen2/3 store dither state in pfit control, needs to match */
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if (DISPLAY_VER(dev_priv) < 4) {
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tmp = intel_de_read(dev_priv, PFIT_CONTROL);
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pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
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crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
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}
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pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
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crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
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}
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static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
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@@ -231,19 +231,19 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
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static void intel_pre_enable_lvds(struct intel_atomic_state *state,
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struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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{
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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enum pipe pipe = crtc->pipe;
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u32 temp;
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if (HAS_PCH_SPLIT(i915)) {
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assert_fdi_rx_pll_disabled(i915, pipe);
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assert_shared_dpll_disabled(i915, pipe_config->shared_dpll);
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assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
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} else {
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assert_pll_disabled(i915, pipe);
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}
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@@ -263,7 +263,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
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/* set the corresponsding LVDS_BORDER bit */
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temp &= ~LVDS_BORDER_ENABLE;
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temp |= pipe_config->gmch_pfit.lvds_border_bits;
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temp |= crtc_state->gmch_pfit.lvds_border_bits;
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/*
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* Set the B0-B3 data pairs corresponding to whether we're going to
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@@ -293,7 +293,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
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* Bspec wording suggests that LVDS port dithering only exists
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* for 18bpp panels.
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*/
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if (pipe_config->dither && pipe_config->pipe_bpp == 18)
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if (crtc_state->dither && crtc_state->pipe_bpp == 18)
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temp |= LVDS_ENABLE_DITHER;
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else
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temp &= ~LVDS_ENABLE_DITHER;
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@@ -312,7 +312,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
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*/
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static void intel_enable_lvds(struct intel_atomic_state *state,
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struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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{
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
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@@ -327,7 +327,7 @@ static void intel_enable_lvds(struct intel_atomic_state *state,
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drm_err(&dev_priv->drm,
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"timed out waiting for panel to power on\n");
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intel_backlight_enable(pipe_config, conn_state);
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intel_backlight_enable(crtc_state, conn_state);
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}
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static void intel_disable_lvds(struct intel_atomic_state *state,
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@@ -407,14 +407,14 @@ intel_lvds_mode_valid(struct drm_connector *_connector,
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}
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static int intel_lvds_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
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struct intel_connector *connector = lvds_encoder->attached_connector;
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struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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unsigned int lvds_bpp;
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int ret;
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@@ -429,14 +429,14 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
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else
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lvds_bpp = 6*3;
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if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
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if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
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drm_dbg_kms(&i915->drm,
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"forcing display bpp (was %d) to LVDS (%d)\n",
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pipe_config->pipe_bpp, lvds_bpp);
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pipe_config->pipe_bpp = lvds_bpp;
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crtc_state->pipe_bpp, lvds_bpp);
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crtc_state->pipe_bpp = lvds_bpp;
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}
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
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/*
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* We have timings from the BIOS for the panel, put them in
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@@ -452,9 +452,9 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
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return -EINVAL;
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if (HAS_PCH_SPLIT(i915))
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pipe_config->has_pch_encoder = true;
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crtc_state->has_pch_encoder = true;
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ret = intel_panel_fitting(pipe_config, conn_state);
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ret = intel_panel_fitting(crtc_state, conn_state);
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if (ret)
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return ret;
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