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clk: clocking-wizard: Fix the round rate handling for versal

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Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.

Fixes: 7681f64e64 ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20250625054114.28273-1-shubhrajyoti.datta@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Shubhrajyoti Datta
2025-06-25 11:11:14 +05:30
committed by Stephen Boyd
parent 264200cc3a
commit 7f5e9ca0a4
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
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@@ -669,7 +669,7 @@ static long clk_wzrd_ver_round_rate_all(struct clk_hw *hw, unsigned long rate,
u32 m, d, o, div, f;
int err;
err = clk_wzrd_get_divisors(hw, rate, *prate);
err = clk_wzrd_get_divisors_ver(hw, rate, *prate);
if (err)
return err;