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x86/cpu/intel: Fix the MOVSL alignment preference for extended Families

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The alignment preference for 32-bit MOVSL based bulk memory move has
been 8-byte for a long time. However this preference is only set for
Family 6 and 15 processors.

Use the same preference for upcoming Family numbers 18 and 19. Also, use
a simpler VFM based check instead of switching based on Family numbers.
Refresh the comment to reflect the new check.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250219184133.816753-3-sohil.mehta@intel.com
This commit is contained in:
Sohil Mehta
2025-02-19 18:41:20 +00:00
committed by Ingo Molnar
parent 680d9b2a56
commit 7e67f36172
1 changed files with 6 additions and 13 deletions
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19
arch/x86/kernel/cpu/intel.c
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@@ -440,23 +440,16 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
(c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
set_cpu_bug(c, X86_BUG_11AP);
#ifdef CONFIG_X86_INTEL_USERCOPY
/*
* Set up the preferred alignment for movsl bulk memory moves
* MOVSL bulk memory moves can be slow when source and dest are not
* both 8-byte aligned. PII/PIII only like MOVSL with 8-byte alignment.
*
* Set the preferred alignment for Pentium Pro and newer processors, as
* it has only been tested on these.
*/
switch (c->x86) {
case 4: /* 486: untested */
break;
case 5: /* Old Pentia: untested */
break;
case 6: /* PII/PIII only like movsl with 8-byte alignment */
if (c->x86_vfm >= INTEL_PENTIUM_PRO)
movsl_mask.mask = 7;
break;
case 15: /* P4 is OK down to 8-byte alignment */
movsl_mask.mask = 7;
break;
}
#endif
intel_smp_check(c);