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ASoC: Intel: catpt: Complete coredump handling

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An exception may occur during the firmware booting procedure.  In such
case the firmware sends COREDUMP_REQUESTS and expects the driver to dump
relevant information and finish with the COREDUMP_RELEASE write.

To distinguish such situation from generic timeout, always signal
fw_ready completion when a coredump request is received and translate
it to -EREMOTEIO in catpt_boot_firmware().

The "FW READY" print makes the success clearly visible even when
the event-traces are not enabled.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://patch.msgid.link/20260528083444.1439233-2-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski
2026-05-28 10:34:42 +02:00
committed by Mark Brown
parent e7ae89a0c9
commit 7e5d59f407
3 changed files with 23 additions and 0 deletions
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8
sound/soc/intel/catpt/ipc.c
View File

@@ -210,6 +210,7 @@ static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)
memcpy_fromio(&config, cdev->lpe_ba + off, sizeof(config));
trace_catpt_ipc_payload((u8 *)&config, sizeof(config));
dev_dbg(cdev->dev, "FW READY 0x%08x\n", header);
catpt_ipc_arm(ipc, &config);
complete(&cdev->fw_ready);
return;
@@ -220,6 +221,13 @@ static void catpt_dsp_process_response(struct catpt_dev *cdev, u32 header)
dev_err(cdev->dev, "ADSP device coredump received\n");
ipc->ready = false;
catpt_coredump(cdev);
if (catpt_readl_dram(cdev, COREDUMP) == CATPT_COREDUMP_REQUEST) {
dev_dbg(cdev->dev, "releasing firmware from the coredump state\n");
catpt_writel_dram(cdev, COREDUMP, CATPT_COREDUMP_RELEASE);
}
complete(&cdev->fw_ready);
/* TODO: attempt recovery */
break;

3
sound/soc/intel/catpt/loader.c
View File

@@ -624,6 +624,9 @@ int catpt_boot_firmware(struct catpt_dev *cdev, bool restore)
if (!ret) {
dev_err(cdev->dev, "firmware ready timeout\n");
return -ETIMEDOUT;
/* Wake up does not mean FW is ready, an exception could occur. */
} else if (!cdev->ipc.ready) {
return -EREMOTEIO;
}
/* update sram pg & clock once done booting */

12
sound/soc/intel/catpt/registers.h
View File

@@ -124,6 +124,11 @@
#define CATPT_SSCR2_DEFAULT 0x0
#define CATPT_SSPSP2_DEFAULT 0x0
/* Coredump register and its states */
#define CATPT_DRAM_COREDUMP 0x1F4
#define CATPT_COREDUMP_REQUEST UINT_MAX
#define CATPT_COREDUMP_RELEASE 0
/* Physically the same block, access address differs between host and dsp */
#define CATPT_DSP_DRAM_OFFSET 0x400000
#define catpt_to_host_offset(offset) ((offset) & ~(CATPT_DSP_DRAM_OFFSET))
@@ -137,6 +142,8 @@
/* registry I/O helpers */
#define catpt_dram_addr(cdev) \
((cdev)->lpe_ba + (cdev)->spec->host_dram_offset)
#define catpt_shim_addr(cdev) \
((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
#define catpt_dma_addr(cdev, dma) \
@@ -151,6 +158,11 @@
#define catpt_writel_ssp(cdev, ssp, reg, val) \
writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
#define catpt_readl_dram(cdev, reg) \
readl(catpt_dram_addr(cdev) + CATPT_DRAM_##reg)
#define catpt_writel_dram(cdev, reg, val) \
writel(val, catpt_dram_addr(cdev) + CATPT_DRAM_##reg)
#define catpt_readl_shim(cdev, reg) \
readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
#define catpt_writel_shim(cdev, reg, val) \