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wifi: ath12k: add ath12k_hw_regs for IPQ5424

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Add register addresses (ath12k_hw_regs) for ath12k AHB based
WiFi 7 device IPQ5424.

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5332 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ5424 hw1.0 AHB WLAN.WBE.1.6-01275-QCAHKSWPL_SILICONZ-1

Signed-off-by: Saravanakumar Duraisamy <quic_saradura@quicinc.com>
Signed-off-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Rameshkumar Sundaram <rameshkumar.sundaram@oss.qualcomm.com>
Link: https://patch.msgid.link/20260407-ath12k-ipq5424-v5-4-8e96aa660ec4@oss.qualcomm.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Saravanakumar Duraisamy
2026-04-07 10:56:31 +05:30
committed by Jeff Johnson
parent 74f5a619b1
commit 7e2131ba33
4 changed files with 93 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/wireless/ath/ath12k/wifi7/hal.c
View File

@@ -55,7 +55,7 @@ static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = {
.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact),
.tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274,
.hal_params = &ath12k_hw_hal_params_ipq5332,
.hw_regs = NULL,
.hw_regs = &ipq5424_regs,
},
};

3
drivers/net/wireless/ath/ath12k/wifi7/hal.h
View File

@@ -364,6 +364,9 @@
#define HAL_IPQ5332_CE_WFSS_REG_BASE 0x740000
#define HAL_IPQ5332_CE_SIZE 0x100000
#define HAL_IPQ5424_CE_WFSS_REG_BASE 0x200000
#define HAL_IPQ5424_CE_SIZE 0x100000
#define HAL_RX_MAX_BA_WINDOW 256
#define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000)

88
drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c
View File

@@ -484,6 +484,94 @@ const struct ath12k_hw_regs ipq5332_regs = {
HAL_IPQ5332_CE_WFSS_REG_BASE,
};
const struct ath12k_hw_regs ipq5424_regs = {
/* SW2TCL(x) R0 ring configuration address */
.tcl1_ring_id = 0x00000918,
.tcl1_ring_misc = 0x00000920,
.tcl1_ring_tp_addr_lsb = 0x0000092c,
.tcl1_ring_tp_addr_msb = 0x00000930,
.tcl1_ring_consumer_int_setup_ix0 = 0x00000940,
.tcl1_ring_consumer_int_setup_ix1 = 0x00000944,
.tcl1_ring_msi1_base_lsb = 0x00000958,
.tcl1_ring_msi1_base_msb = 0x0000095c,
.tcl1_ring_base_lsb = 0x00000910,
.tcl1_ring_base_msb = 0x00000914,
.tcl1_ring_msi1_data = 0x00000960,
.tcl2_ring_base_lsb = 0x00000988,
.tcl_ring_base_lsb = 0x00000b68,
/* TCL STATUS ring address */
.tcl_status_ring_base_lsb = 0x00000d48,
/* REO DEST ring address */
.reo2_ring_base = 0x00000578,
.reo1_misc_ctrl_addr = 0x00000b9c,
.reo1_sw_cookie_cfg0 = 0x0000006c,
.reo1_sw_cookie_cfg1 = 0x00000070,
.reo1_qdesc_lut_base0 = 0x00000074,
.reo1_qdesc_lut_base1 = 0x00000078,
.reo1_ring_base_lsb = 0x00000500,
.reo1_ring_base_msb = 0x00000504,
.reo1_ring_id = 0x00000508,
.reo1_ring_misc = 0x00000510,
.reo1_ring_hp_addr_lsb = 0x00000514,
.reo1_ring_hp_addr_msb = 0x00000518,
.reo1_ring_producer_int_setup = 0x00000524,
.reo1_ring_msi1_base_lsb = 0x00000548,
.reo1_ring_msi1_base_msb = 0x0000054C,
.reo1_ring_msi1_data = 0x00000550,
.reo1_aging_thres_ix0 = 0x00000B28,
.reo1_aging_thres_ix1 = 0x00000B2C,
.reo1_aging_thres_ix2 = 0x00000B30,
.reo1_aging_thres_ix3 = 0x00000B34,
/* REO Exception ring address */
.reo2_sw0_ring_base = 0x000008c0,
/* REO Reinject ring address */
.sw2reo_ring_base = 0x00000320,
.sw2reo1_ring_base = 0x00000398,
/* REO cmd ring address */
.reo_cmd_ring_base = 0x000002A8,
/* REO status ring address */
.reo_status_ring_base = 0x00000aa0,
/* WBM idle link ring address */
.wbm_idle_ring_base_lsb = 0x00000d3c,
.wbm_idle_ring_misc_addr = 0x00000d4c,
.wbm_r0_idle_list_cntl_addr = 0x00000240,
.wbm_r0_idle_list_size_addr = 0x00000244,
.wbm_scattered_ring_base_lsb = 0x00000250,
.wbm_scattered_ring_base_msb = 0x00000254,
.wbm_scattered_desc_head_info_ix0 = 0x00000260,
.wbm_scattered_desc_head_info_ix1 = 0x00000264,
.wbm_scattered_desc_tail_info_ix0 = 0x00000270,
.wbm_scattered_desc_tail_info_ix1 = 0x00000274,
.wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
/* SW2WBM release ring address */
.wbm_sw_release_ring_base_lsb = 0x0000037c,
/* WBM2SW release ring address */
.wbm0_release_ring_base_lsb = 0x00000e08,
.wbm1_release_ring_base_lsb = 0x00000e80,
/* PPE release ring address */
.ppe_rel_ring_base = 0x0000046c,
/* CE address */
.umac_ce0_src_reg_base = 0x00200000 -
HAL_IPQ5424_CE_WFSS_REG_BASE,
.umac_ce0_dest_reg_base = 0x00201000 -
HAL_IPQ5424_CE_WFSS_REG_BASE,
.umac_ce1_src_reg_base = 0x00202000 -
HAL_IPQ5424_CE_WFSS_REG_BASE,
.umac_ce1_dest_reg_base = 0x00203000 -
HAL_IPQ5424_CE_WFSS_REG_BASE,
};
static inline
bool ath12k_hal_rx_desc_get_first_msdu_qcn9274(struct hal_rx_desc *desc)
{

1
drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h
View File

@@ -17,6 +17,7 @@ extern const struct hal_ops hal_qcn9274_ops;
extern const struct ath12k_hw_regs qcn9274_v1_regs;
extern const struct ath12k_hw_regs qcn9274_v2_regs;
extern const struct ath12k_hw_regs ipq5332_regs;
extern const struct ath12k_hw_regs ipq5424_regs;
extern const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_tcl_to_wbm_rbm_map_qcn9274[DP_TCL_NUM_RING_MAX];
extern const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274;