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ASoC: tegra: ADX: Add Tegra264 support
Add Tegra264 ADX support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 ADX supports 32 input channels, hence update the playback DAI channels_max parameter and CIF configuration API. - Register offsets and default values are updated to align with Tegra264. - Add 128 byte map controls for Tegra264 to accommodate each byte per channel (32channels x 32bits). Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-10-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sheetal
@@ -9,6 +9,7 @@
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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@@ -32,21 +33,37 @@ static const struct reg_default tegra210_adx_reg_defaults[] = {
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{ TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000},
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};
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static const struct reg_default tegra264_adx_reg_defaults[] = {
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{ TEGRA210_ADX_RX_INT_MASK, 0x00000001},
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{ TEGRA210_ADX_RX_CIF_CTRL, 0x00003800},
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{ TEGRA210_ADX_TX_INT_MASK, 0x0000000f },
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{ TEGRA210_ADX_TX1_CIF_CTRL, 0x00003800},
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{ TEGRA210_ADX_TX2_CIF_CTRL, 0x00003800},
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{ TEGRA210_ADX_TX3_CIF_CTRL, 0x00003800},
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{ TEGRA210_ADX_TX4_CIF_CTRL, 0x00003800},
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{ TEGRA210_ADX_CG, 0x1},
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{ TEGRA264_ADX_CFG_RAM_CTRL, 0x00004000},
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};
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static void tegra210_adx_write_map_ram(struct tegra210_adx *adx)
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{
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int i;
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL,
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL +
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adx->soc_data->cya_offset,
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TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
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TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN |
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TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE);
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for (i = 0; i < TEGRA210_ADX_RAM_DEPTH; i++)
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA,
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for (i = 0; i < adx->soc_data->ram_depth; i++)
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA +
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adx->soc_data->cya_offset,
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adx->map[i]);
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regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN0, adx->byte_mask[0]);
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regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN1, adx->byte_mask[1]);
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for (i = 0; i < adx->soc_data->byte_mask_size; i++)
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regmap_write(adx->regmap,
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TEGRA210_ADX_IN_BYTE_EN0 + (i * TEGRA210_ADX_AUDIOCIF_CH_STRIDE),
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adx->byte_mask[i]);
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}
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static int tegra210_adx_startup(struct snd_pcm_substream *substream,
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@@ -117,7 +134,7 @@ static int tegra210_adx_set_audio_cif(struct snd_soc_dai *dai,
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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if (channels < 1 || channels > 16)
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if (channels < 1 || channels > adx->soc_data->max_ch)
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return -EINVAL;
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switch (format) {
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@@ -140,7 +157,10 @@ static int tegra210_adx_set_audio_cif(struct snd_soc_dai *dai,
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra_set_cif(adx->regmap, reg, &cif_conf);
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if (adx->soc_data->max_ch == 32)
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tegra264_set_cif(adx->regmap, reg, &cif_conf);
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else
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tegra_set_cif(adx->regmap, reg, &cif_conf);
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return 0;
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}
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@@ -169,7 +189,7 @@ static int tegra210_adx_get_byte_map(struct snd_kcontrol *kcontrol,
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
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struct soc_mixer_control *mc;
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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unsigned char *bytes_map = (unsigned char *)adx->map;
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int enabled;
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mc = (struct soc_mixer_control *)kcontrol->private_value;
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@@ -198,7 +218,7 @@ static int tegra210_adx_put_byte_map(struct snd_kcontrol *kcontrol,
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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unsigned char *bytes_map = (unsigned char *)adx->map;
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int value = ucontrol->value.integer.value[0];
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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@@ -402,7 +422,90 @@ static struct snd_kcontrol_new tegra210_adx_controls[] = {
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TEGRA210_ADX_BYTE_MAP_CTRL(63),
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};
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static struct snd_kcontrol_new tegra264_adx_controls[] = {
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TEGRA210_ADX_BYTE_MAP_CTRL(64),
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TEGRA210_ADX_BYTE_MAP_CTRL(65),
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TEGRA210_ADX_BYTE_MAP_CTRL(66),
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TEGRA210_ADX_BYTE_MAP_CTRL(67),
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TEGRA210_ADX_BYTE_MAP_CTRL(68),
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TEGRA210_ADX_BYTE_MAP_CTRL(69),
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TEGRA210_ADX_BYTE_MAP_CTRL(70),
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TEGRA210_ADX_BYTE_MAP_CTRL(71),
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TEGRA210_ADX_BYTE_MAP_CTRL(72),
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TEGRA210_ADX_BYTE_MAP_CTRL(73),
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TEGRA210_ADX_BYTE_MAP_CTRL(74),
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TEGRA210_ADX_BYTE_MAP_CTRL(75),
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TEGRA210_ADX_BYTE_MAP_CTRL(76),
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TEGRA210_ADX_BYTE_MAP_CTRL(77),
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TEGRA210_ADX_BYTE_MAP_CTRL(78),
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TEGRA210_ADX_BYTE_MAP_CTRL(79),
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TEGRA210_ADX_BYTE_MAP_CTRL(80),
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TEGRA210_ADX_BYTE_MAP_CTRL(81),
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TEGRA210_ADX_BYTE_MAP_CTRL(82),
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TEGRA210_ADX_BYTE_MAP_CTRL(83),
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TEGRA210_ADX_BYTE_MAP_CTRL(84),
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TEGRA210_ADX_BYTE_MAP_CTRL(85),
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TEGRA210_ADX_BYTE_MAP_CTRL(86),
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TEGRA210_ADX_BYTE_MAP_CTRL(87),
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TEGRA210_ADX_BYTE_MAP_CTRL(88),
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TEGRA210_ADX_BYTE_MAP_CTRL(89),
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TEGRA210_ADX_BYTE_MAP_CTRL(90),
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TEGRA210_ADX_BYTE_MAP_CTRL(91),
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TEGRA210_ADX_BYTE_MAP_CTRL(92),
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TEGRA210_ADX_BYTE_MAP_CTRL(93),
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TEGRA210_ADX_BYTE_MAP_CTRL(94),
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TEGRA210_ADX_BYTE_MAP_CTRL(95),
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TEGRA210_ADX_BYTE_MAP_CTRL(96),
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TEGRA210_ADX_BYTE_MAP_CTRL(97),
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TEGRA210_ADX_BYTE_MAP_CTRL(98),
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TEGRA210_ADX_BYTE_MAP_CTRL(99),
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TEGRA210_ADX_BYTE_MAP_CTRL(100),
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TEGRA210_ADX_BYTE_MAP_CTRL(101),
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TEGRA210_ADX_BYTE_MAP_CTRL(102),
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TEGRA210_ADX_BYTE_MAP_CTRL(103),
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TEGRA210_ADX_BYTE_MAP_CTRL(104),
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TEGRA210_ADX_BYTE_MAP_CTRL(105),
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TEGRA210_ADX_BYTE_MAP_CTRL(106),
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TEGRA210_ADX_BYTE_MAP_CTRL(107),
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TEGRA210_ADX_BYTE_MAP_CTRL(108),
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TEGRA210_ADX_BYTE_MAP_CTRL(109),
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TEGRA210_ADX_BYTE_MAP_CTRL(110),
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TEGRA210_ADX_BYTE_MAP_CTRL(111),
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TEGRA210_ADX_BYTE_MAP_CTRL(112),
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TEGRA210_ADX_BYTE_MAP_CTRL(113),
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TEGRA210_ADX_BYTE_MAP_CTRL(114),
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TEGRA210_ADX_BYTE_MAP_CTRL(115),
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TEGRA210_ADX_BYTE_MAP_CTRL(116),
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TEGRA210_ADX_BYTE_MAP_CTRL(117),
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TEGRA210_ADX_BYTE_MAP_CTRL(118),
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TEGRA210_ADX_BYTE_MAP_CTRL(119),
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TEGRA210_ADX_BYTE_MAP_CTRL(120),
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TEGRA210_ADX_BYTE_MAP_CTRL(121),
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TEGRA210_ADX_BYTE_MAP_CTRL(122),
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TEGRA210_ADX_BYTE_MAP_CTRL(123),
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TEGRA210_ADX_BYTE_MAP_CTRL(124),
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TEGRA210_ADX_BYTE_MAP_CTRL(125),
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TEGRA210_ADX_BYTE_MAP_CTRL(126),
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TEGRA210_ADX_BYTE_MAP_CTRL(127),
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};
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static int tegra210_adx_component_probe(struct snd_soc_component *component)
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{
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struct tegra210_adx *adx = snd_soc_component_get_drvdata(component);
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int err = 0;
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if (adx->soc_data->num_controls) {
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err = snd_soc_add_component_controls(component, adx->soc_data->controls,
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adx->soc_data->num_controls);
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if (err)
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dev_err(component->dev, "can't add ADX controls, err: %d\n", err);
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}
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return err;
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}
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static const struct snd_soc_component_driver tegra210_adx_cmpnt = {
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.probe = tegra210_adx_component_probe,
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.dapm_widgets = tegra210_adx_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_adx_widgets),
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.dapm_routes = tegra210_adx_routes,
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@@ -460,6 +563,58 @@ static bool tegra210_adx_volatile_reg(struct device *dev,
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return false;
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}
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static bool tegra264_adx_wr_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_ADX_TX_INT_MASK ... TEGRA210_ADX_TX4_CIF_CTRL:
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case TEGRA210_ADX_RX_INT_MASK ... TEGRA210_ADX_RX_CIF_CTRL:
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case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_CG:
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case TEGRA210_ADX_CTRL ... TEGRA264_ADX_CYA:
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case TEGRA264_ADX_CFG_RAM_CTRL ... TEGRA264_ADX_CFG_RAM_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra264_adx_rd_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_ADX_RX_STATUS ... TEGRA210_ADX_RX_CIF_CTRL:
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case TEGRA210_ADX_TX_STATUS ... TEGRA210_ADX_TX4_CIF_CTRL:
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case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_INT_STATUS:
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case TEGRA210_ADX_CTRL ... TEGRA264_ADX_CFG_RAM_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra264_adx_volatile_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_ADX_RX_STATUS:
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case TEGRA210_ADX_RX_INT_STATUS:
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case TEGRA210_ADX_RX_INT_SET:
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case TEGRA210_ADX_TX_STATUS:
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case TEGRA210_ADX_TX_INT_STATUS:
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case TEGRA210_ADX_TX_INT_SET:
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case TEGRA210_ADX_SOFT_RESET:
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case TEGRA210_ADX_STATUS:
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case TEGRA210_ADX_INT_STATUS:
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case TEGRA264_ADX_CFG_RAM_CTRL:
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case TEGRA264_ADX_CFG_RAM_DATA:
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return true;
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default:
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break;
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}
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return false;
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}
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static const struct regmap_config tegra210_adx_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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@@ -473,8 +628,40 @@ static const struct regmap_config tegra210_adx_regmap_config = {
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.cache_type = REGCACHE_FLAT,
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};
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static const struct regmap_config tegra264_adx_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = TEGRA264_ADX_CFG_RAM_DATA,
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.writeable_reg = tegra264_adx_wr_reg,
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.readable_reg = tegra264_adx_rd_reg,
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.volatile_reg = tegra264_adx_volatile_reg,
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.reg_defaults = tegra264_adx_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tegra264_adx_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static const struct tegra210_adx_soc_data soc_data_tegra210 = {
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.regmap_conf = &tegra210_adx_regmap_config,
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.max_ch = TEGRA210_ADX_MAX_CHANNEL,
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.ram_depth = TEGRA210_ADX_RAM_DEPTH,
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.byte_mask_size = TEGRA210_ADX_BYTE_MASK_COUNT,
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.cya_offset = TEGRA210_ADX_CYA_OFFSET,
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};
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static const struct tegra210_adx_soc_data soc_data_tegra264 = {
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.regmap_conf = &tegra264_adx_regmap_config,
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.max_ch = TEGRA264_ADX_MAX_CHANNEL,
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.ram_depth = TEGRA264_ADX_RAM_DEPTH,
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.byte_mask_size = TEGRA264_ADX_BYTE_MASK_COUNT,
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.cya_offset = TEGRA264_ADX_CYA_OFFSET,
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.controls = tegra264_adx_controls,
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.num_controls = ARRAY_SIZE(tegra264_adx_controls),
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};
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static const struct of_device_id tegra210_adx_of_match[] = {
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{ .compatible = "nvidia,tegra210-adx" },
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{ .compatible = "nvidia,tegra210-adx", .data = &soc_data_tegra210 },
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{ .compatible = "nvidia,tegra264-adx", .data = &soc_data_tegra264 },
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{},
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};
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MODULE_DEVICE_TABLE(of, tegra210_adx_of_match);
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@@ -483,6 +670,8 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct tegra210_adx *adx;
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const struct of_device_id *match;
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struct tegra210_adx_soc_data *soc_data;
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void __iomem *regs;
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int err;
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@@ -490,6 +679,10 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)
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if (!adx)
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return -ENOMEM;
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match = of_match_device(tegra210_adx_of_match, dev);
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soc_data = (struct tegra210_adx_soc_data *)match->data;
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adx->soc_data = soc_data;
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dev_set_drvdata(dev, adx);
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regs = devm_platform_ioremap_resource(pdev, 0);
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@@ -497,7 +690,7 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)
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return PTR_ERR(regs);
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adx->regmap = devm_regmap_init_mmio(dev, regs,
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&tegra210_adx_regmap_config);
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soc_data->regmap_conf);
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if (IS_ERR(adx->regmap)) {
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dev_err(dev, "regmap init failed\n");
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return PTR_ERR(adx->regmap);
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@@ -505,6 +698,20 @@ static int tegra210_adx_platform_probe(struct platform_device *pdev)
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regcache_cache_only(adx->regmap, true);
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adx->map = devm_kzalloc(dev, soc_data->ram_depth * sizeof(*adx->map),
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GFP_KERNEL);
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if (!adx->map)
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return -ENOMEM;
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adx->byte_mask = devm_kzalloc(dev,
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soc_data->byte_mask_size * sizeof(*adx->byte_mask),
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GFP_KERNEL);
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if (!adx->byte_mask)
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return -ENOMEM;
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tegra210_adx_dais[TEGRA_ADX_IN_DAI_ID].playback.channels_max =
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adx->soc_data->max_ch;
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err = devm_snd_soc_register_component(dev, &tegra210_adx_cmpnt,
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tegra210_adx_dais,
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ARRAY_SIZE(tegra210_adx_dais));
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@@ -1,8 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_adx.h - Definitions for Tegra210 ADX driver
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/* SPDX-License-Identifier: GPL-2.0-only
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* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved.
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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* tegra210_adx.h - Definitions for Tegra210 ADX driver
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*
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*/
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@@ -36,6 +35,10 @@
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#define TEGRA210_ADX_CFG_RAM_CTRL 0xb8
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#define TEGRA210_ADX_CFG_RAM_DATA 0xbc
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#define TEGRA264_ADX_CYA 0xb8
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#define TEGRA264_ADX_CFG_RAM_CTRL 0xc0
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#define TEGRA264_ADX_CFG_RAM_DATA 0xc4
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/* Fields in TEGRA210_ADX_ENABLE */
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#define TEGRA210_ADX_ENABLE_SHIFT 0
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@@ -62,11 +65,32 @@
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#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6
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#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2
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#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0
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#define TEGRA210_ADX_BYTE_MASK_COUNT 2
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#define TEGRA210_ADX_MAX_CHANNEL 16
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#define TEGRA210_ADX_CYA_OFFSET 0
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#define TEGRA264_ADX_RAM_DEPTH 32
|
||||
#define TEGRA264_ADX_BYTE_MASK_COUNT 4
|
||||
#define TEGRA264_ADX_MAX_CHANNEL 32
|
||||
#define TEGRA264_ADX_CYA_OFFSET 8
|
||||
|
||||
#define TEGRA_ADX_IN_DAI_ID 4
|
||||
|
||||
struct tegra210_adx_soc_data {
|
||||
const struct regmap_config *regmap_conf;
|
||||
const struct snd_kcontrol_new *controls;
|
||||
unsigned int num_controls;
|
||||
unsigned int max_ch;
|
||||
unsigned int ram_depth;
|
||||
unsigned int byte_mask_size;
|
||||
unsigned int cya_offset;
|
||||
};
|
||||
|
||||
struct tegra210_adx {
|
||||
struct regmap *regmap;
|
||||
unsigned int map[TEGRA210_ADX_RAM_DEPTH];
|
||||
unsigned int byte_mask[2];
|
||||
unsigned int *map;
|
||||
unsigned int *byte_mask;
|
||||
const struct tegra210_adx_soc_data *soc_data;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user