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x86/mtrr: Disentangle MTRR init from PAT init

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Add a main cache_cpu_init() init routine which initializes MTRR and/or
PAT support depending on what has been detected on the system.

Leave the MTRR-specific initialization in a MTRR-specific init function
where the smp_changes_mask setting happens now with caches disabled.

This global mask update was done with caches enabled before probably
because atomic operations while running uncached might have been quite
expensive.

But since only systems with a broken BIOS should ever require to set any
bit in smp_changes_mask, hurting those devices with a penalty of a few
microseconds during boot shouldn't be a real issue.

Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20221102074713.21493-8-jgross@suse.com
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Juergen Gross
2022-11-02 08:47:04 +01:00
committed by Borislav Petkov
parent 23a63e3690
commit 7d71db537b
4 changed files with 22 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/x86/include/asm/cacheinfo.h
View File

@@ -12,5 +12,6 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);
void cache_disable(void);
void cache_enable(void);
void cache_cpu_init(void);
#endif /* _ASM_X86_CACHEINFO_H */

2
arch/x86/include/asm/mtrr.h
View File

@@ -50,6 +50,7 @@ extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
extern int amd_special_default_mtrr(void);
void mtrr_disable(void);
void mtrr_enable(void);
void mtrr_generic_set_state(void);
# else
static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform)
{
@@ -91,6 +92,7 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
#define mtrr_bp_restore() do {} while (0)
#define mtrr_disable() do {} while (0)
#define mtrr_enable() do {} while (0)
#define mtrr_generic_set_state() do {} while (0)
# endif
#ifdef CONFIG_COMPAT

17
arch/x86/kernel/cpu/cacheinfo.c
View File

@@ -1120,3 +1120,20 @@ void cache_enable(void) __releases(cache_disable_lock)
raw_spin_unlock(&cache_disable_lock);
}
void cache_cpu_init(void)
{
unsigned long flags;
local_irq_save(flags);
cache_disable();
if (memory_caching_control & CACHE_MTRR)
mtrr_generic_set_state();
if (memory_caching_control & CACHE_PAT)
pat_init();
cache_enable();
local_irq_restore(flags);
}

15
arch/x86/kernel/cpu/mtrr/generic.c
View File

@@ -731,30 +731,19 @@ void mtrr_enable(void)
mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
}
static void generic_set_all(void)
void mtrr_generic_set_state(void)
{
unsigned long mask, count;
unsigned long flags;
local_irq_save(flags);
cache_disable();
/* Actually set the state */
mask = set_mtrr_state();
/* also set PAT */
pat_init();
cache_enable();
local_irq_restore(flags);
/* Use the atomic bitops to update the global mask */
for (count = 0; count < sizeof(mask) * 8; ++count) {
if (mask & 0x01)
set_bit(count, &smp_changes_mask);
mask >>= 1;
}
}
/**
@@ -854,7 +843,7 @@ int positive_have_wrcomb(void)
* Generic structure...
*/
const struct mtrr_ops generic_mtrr_ops = {
.set_all = generic_set_all,
.set_all = cache_cpu_init,
.get = generic_get_mtrr,
.get_free_region = generic_get_free_region,
.set = generic_set_mtrr,