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staging: comedi: addi_apci_3120: define the timer 2 operation bits
For aesthetics, redefine the bits in the mode register used to set the operation mode of timer 2. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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committed by
Greg Kroah-Hartman
parent
1869ae026c
commit
7cbc057d85
@@ -101,8 +101,6 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY
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#define APCI3120_WRITE_MODE_SELECT 0x0e
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#define APCI3120_RD_STATUS 0x02
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#define APCI3120_ENABLE_WATCHDOG 0x20
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#define APCI3120_ENABLE_TIMER_COUNTER 0x10
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#define APCI3120_FC_TIMER 0x1000
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#define APCI3120_TIMER2_SELECT_EOS 0xc0
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@@ -564,7 +562,7 @@ static int apci3120_cyclic_ai(int mode,
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apci3120_clr_timer2_interrupt(dev);
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/* enable timer counter and disable watch dog */
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devpriv->mode |= APCI3120_ENABLE_TIMER_COUNTER;
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devpriv->mode |= APCI3120_MODE_TIMER2_AS_COUNTER;
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/* select EOS clock input for timer 2 */
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devpriv->mode |= APCI3120_TIMER2_SELECT_EOS;
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/* Enable timer2 interrupt */
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@@ -1081,9 +1079,9 @@ static int apci3120_config_insn_timer(struct comedi_device *dev,
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apci3120_timer_enable(dev, 2, false);
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/* Disable TIMER Interrupt */
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/* disable timer 2 interrupt and reset operation mode (timer) */
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devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA &
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~APCI3120_ENABLE_TIMER_COUNTER;
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~APCI3120_MODE_TIMER2_AS_MASK;
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/* Disable Eoc and Eos Interrupts */
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devpriv->mode &= ~APCI3120_MODE_EOC_IRQ_ENA &
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@@ -1156,10 +1154,11 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
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if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */
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/* Enable Timer */
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devpriv->mode &= 0x0b;
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devpriv->mode |= APCI3120_MODE_TIMER2_AS_TIMER;
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} else { /* start watch dog */
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/* Enable WatchDog */
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devpriv->mode &= 0x0b;
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devpriv->mode |= APCI3120_ENABLE_WATCHDOG;
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devpriv->mode |= APCI3120_MODE_TIMER2_AS_WDOG;
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}
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/* enable disable interrupt */
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@@ -1179,15 +1178,9 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
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break;
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case APCI3120_STOP:
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if (devpriv->b_Timer2Mode == APCI3120_TIMER) {
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/* Disable timer */
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devpriv->mode &= ~APCI3120_ENABLE_TIMER_COUNTER;
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} else {
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/* Disable WatchDog */
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devpriv->mode &= ~APCI3120_ENABLE_WATCHDOG;
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}
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/* Disable timer interrupt */
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devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA;
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/* disable timer 2 interrupt and reset operation mode (timer) */
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devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA &
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~APCI3120_MODE_TIMER2_AS_MASK;
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outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
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apci3120_timer_enable(dev, 2, false);
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@@ -40,6 +40,10 @@
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#define APCI3120_CTR0_REG 0x0d
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#define APCI3120_CTR0_DO_BITS(x) ((x) << 4)
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#define APCI3120_CTR0_TIMER_SEL(x) ((x) << 0)
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#define APCI3120_MODE_TIMER2_AS_TIMER (0 << 4)
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#define APCI3120_MODE_TIMER2_AS_COUNTER (1 << 4)
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#define APCI3120_MODE_TIMER2_AS_WDOG (2 << 4)
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#define APCI3120_MODE_TIMER2_AS_MASK (3 << 4) /* sets AS_TIMER */
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#define APCI3120_MODE_SCAN_ENA (1 << 3)
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#define APCI3120_MODE_TIMER2_IRQ_ENA (1 << 2)
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#define APCI3120_MODE_EOS_IRQ_ENA (1 << 1)
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