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drm/i915: Add a separate definition for PIPE_CRC_RES_HSW

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On hsw+ we only have one CRC result register, instead of the
five we have on ivb, and some of the others have been repurposed
to serve other CRC related purposes.

Since the hsw+ vs. pre-hsw register operate quite differently
let's add a separate definition for the hsw+ variant to make the
situation a bit more clear. Also since we only use this from a
hsw+ codepath there is no real benefit to be had with reusing
the ivb register definition.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2024-05-31 14:53:39 +03:00
parent 1ec6defe71
commit 7bd7cfa833
2 changed files with 6 additions and 1 deletions
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2
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
display_pipe_crc_irq_handler(dev_priv, pipe,
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)),
0, 0, 0, 0);
}

5
drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
View File

@@ -92,4 +92,9 @@
#define _PIPE_CRC_RES_5_B_IVB 0x61074
#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
/* hsw+ */
#define _PIPE_CRC_RES_A_HSW 0x60064
#define _PIPE_CRC_RES_B_HSW 0x61064
#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
#endif /* __INTEL_PIPE_CRC_REGS_H__ */